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[PULL 35/47] target/ppc: Improve timebase register defines naming
From: |
Nicholas Piggin |
Subject: |
[PULL 35/47] target/ppc: Improve timebase register defines naming |
Date: |
Sat, 24 Feb 2024 01:41:54 +1000 |
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.
The ISA changed around v2.03 to bring TB and TBU reads into the SPR
space at 268 and 269 (access via mftb TBR-space is still supported
but will be phased out). Later, VTB was added which is an entirely
different register.
The SPR number defines in QEMU are understandably inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 8 ++++----
target/ppc/helper_regs.c | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a44de22ca4..16baea609c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1750,8 +1750,8 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_USPRG5 (0x105)
#define SPR_USPRG6 (0x106)
#define SPR_USPRG7 (0x107)
-#define SPR_VTBL (0x10C)
-#define SPR_VTBU (0x10D)
+#define SPR_TBL (0x10C)
+#define SPR_TBU (0x10D)
#define SPR_SPRG0 (0x110)
#define SPR_SPRG1 (0x111)
#define SPR_SPRG2 (0x112)
@@ -1764,8 +1764,8 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_SPRG7 (0x117)
#define SPR_ASR (0x118)
#define SPR_EAR (0x11A)
-#define SPR_TBL (0x11C)
-#define SPR_TBU (0x11D)
+#define SPR_WR_TBL (0x11C)
+#define SPR_WR_TBU (0x11D)
#define SPR_TBU40 (0x11E)
#define SPR_SVR (0x11E)
#define SPR_BOOKE_PIR (0x11E)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 8f5bd1536e..94c9a5a5c1 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -461,22 +461,22 @@ void register_generic_sprs(PowerPCCPU *cpu)
/* Time base */
#if defined(TARGET_PPC64)
- spr_register(env, SPR_VTBL, "TB",
+ spr_register(env, SPR_TBL, "TB",
#else
- spr_register(env, SPR_VTBL, "TBL",
+ spr_register(env, SPR_TBL, "TBL",
#endif
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_TBL, "TBL",
+ spr_register(env, SPR_WR_TBL, "TBL",
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, &spr_write_tbl,
0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
+ spr_register(env, SPR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_TBU, "TBU",
+ spr_register(env, SPR_WR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, &spr_write_tbu,
0x00000000);
--
2.42.0
- [PULL 03/47] tests/avocado: mark boot_linux.py long runtime instead of flaky, (continued)
- [PULL 03/47] tests/avocado: mark boot_linux.py long runtime instead of flaky, Nicholas Piggin, 2024/02/23
- [PULL 06/47] tests/avocado: Add ppc pseries and powernv hash MMU tests, Nicholas Piggin, 2024/02/23
- [PULL 20/47] ppc/pnv: Change powernv default to powernv10, Nicholas Piggin, 2024/02/23
- [PULL 22/47] misc/pca9552: Let external devices set pca9552 inputs, Nicholas Piggin, 2024/02/23
- [PULL 24/47] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control, Nicholas Piggin, 2024/02/23
- [PULL 11/47] target/ppc: Rename registers to match ISA, Nicholas Piggin, 2024/02/23
- [PULL 17/47] ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS., Nicholas Piggin, 2024/02/23
- [PULL 19/47] spapr: Tag pseries-2.1 - 2.11 machines as deprecated, Nicholas Piggin, 2024/02/23
- [PULL 29/47] ppc/pnv: Test pnv i2c master and connected devices, Nicholas Piggin, 2024/02/23
- [PULL 32/47] hw/ppc: N1 chiplet wiring, Nicholas Piggin, 2024/02/23
- [PULL 35/47] target/ppc: Improve timebase register defines naming,
Nicholas Piggin <=
- [PULL 33/47] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U, Nicholas Piggin, 2024/02/23
- [PULL 37/47] ppc/pnv: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/02/23
- [PULL 05/47] tests/avocado: ppc add powernv10 boot_linux_console test, Nicholas Piggin, 2024/02/23
- [PULL 16/47] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs., Nicholas Piggin, 2024/02/23
- [PULL 18/47] ppc/spapr: change pseries machine default to POWER10 CPU, Nicholas Piggin, 2024/02/23
- [PULL 25/47] ppc/pnv: Wire up pca9552 GPIO pins for PCIe hotplug power control, Nicholas Piggin, 2024/02/23
- [PULL 26/47] ppc/pnv: Use resettable interface to reset child I2C buses, Nicholas Piggin, 2024/02/23
- [PULL 28/47] ppc/pnv: Add a pca9554 I2C device to powernv10-rainier, Nicholas Piggin, 2024/02/23
- [PULL 30/47] hw/ppc: Add pnv nest pervasive common chiplet model, Nicholas Piggin, 2024/02/23
- [PULL 43/47] target/ppc: Factor out 4xx ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/23