[Commit-gnuradio] [gnuradio] 104/148: barebones udp support. Compiles, but untested.

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nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.

commit a4779f73842e20c0d472859ca9ef40f4f0171690
Author: Matt Ettus <address@hidden>
Date:   Fri Sep 11 01:05:24 2009 -0700

    barebones udp support.  Compiles, but untested.
---
 usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v   |  29 ++--
 usrp2/fpga/top/u2_core/u2_core.v                   |  17 ++-
 usrp2/fpga/top/u2_rev3/Makefile                    |  13 +-
 usrp2/fpga/udp/add_onescomp.v                      |  12 ++
 .../newfifo => udp}/fifo19_rxrealign.v             |   0
 usrp2/fpga/udp/prot_eng_rx.v                       | 121 +++++++++++++++
 usrp2/fpga/udp/prot_eng_tx.v                       | 119 +++++++++++++++
 usrp2/fpga/udp/prot_eng_tx_tb.v                    | 167 +++++++++++++++++++++
 usrp2/fpga/udp/udp_wrapper.v                       |  78 ++++++++++
 9 files changed, 538 insertions(+), 18 deletions(-)

diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v 
b/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v
index 96f1c01..11cf7ee 100644
--- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v
@@ -9,7 +9,7 @@ module simple_gemac_wrapper19
     
     // Client FIFO Interfaces
     input sys_clk,
-    output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
+    output [18:0] rx_f19_data, output rx_f19_src_rdy, input rx_f19_dst_rdy,
     input [18:0] tx_f19_data, input tx_f19_src_rdy, output tx_f19_dst_rdy,
     
     // Wishbone Interface
@@ -69,8 +69,8 @@ module simple_gemac_wrapper19
    
    wire [7:0]    rx_ll_data, rx_ll_data2;
    
-   wire [35:0]           rx_f36_data_int1;
-   wire          rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+   wire [18:0]           rx_f19_data_int1;
+   wire          rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1;
    
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -90,17 +90,17 @@ module simple_gemac_wrapper19
    assign rx_ll_sof2_n           = ~rx_ll_sof2;
    assign rx_ll_eof2_n           = ~rx_ll_eof2;
    
-   ll8_to_fifo36 ll8_to_fifo36
+   ll8_to_fifo19 ll8_to_fifo19
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
       .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
       .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
-      .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), 
.f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+      .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), 
.f19_dst_rdy_i(rx_f19_dst_rdy_int1));
 
-   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
-     (.wclk(rx_clk), .datain(rx_f36_data_int1), 
-      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), 
.space(rx_fifo_space),
-      .rclk(sys_clk), .dataout(rx_f36_data), 
-      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), 
.arst(reset));
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+     (.wclk(rx_clk), .datain(rx_f19_data_int1), 
+      .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), 
.space(rx_fifo_space),
+      .rclk(sys_clk), .dataout(rx_f19_data), 
+      .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), 
.arst(reset));
    
    // TX FIFO Chain
    wire          tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
@@ -147,7 +147,8 @@ module simple_gemac_wrapper19
       .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), 
.pause_time_req(pause_time_req));
    
    wire [31:0]           debug_tx, debug_rx;
-   
+
+   /*
    assign debug_tx  = { { tx_ll_data },
                        { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
                          tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, 
tx_ll_dst_rdy2 },
@@ -156,9 +157,9 @@ module simple_gemac_wrapper19
    assign debug_rx  = { { rx_ll_data },
                        { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
                          rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, 
rx_ll_dst_rdy2 },
-                       { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, 
rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
+                       { rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, 
rx_f19_dst_rdy_int1, rx_f19_data_int1[34:32]},
                        { rx_data} };
-
+    */
    assign debug  = debug_rx;
    
-endmodule // simple_gemac_wrapper18
+endmodule // simple_gemac_wrapper19
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index fd17a10..5b52483 100755
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -412,19 +412,30 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
-   simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper
+   wire [18:0]          rx_f19_data, tx_f19_data;
+   wire         rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   
+   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) 
simple_gemac_wrapper19
      (.clk125(clk_to_mac),  .reset(wb_rst),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .sys_clk(dsp_clk),
-      .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), 
.rx_f36_dst_rdy(wr2_ready_o),
-      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), 
.tx_f36_dst_rdy(rd2_ready_i),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), 
.rx_f19_dst_rdy(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), 
.tx_f19_dst_rdy(tx_f19_dst_rdy),
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), 
.wb_ack(s6_ack),
       .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
       .mdio(MDIO), .mdc(MDC),
       .debug(debug_mac));
+
+   udp_wrapper #(.BASE(0)) udp_wrapper
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), 
.rx_f19_dst_rdy_o(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), 
.tx_f19_dst_rdy_i(tx_f19_dst_rdy),
+      .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), 
.rx_f36_dst_rdy_i(wr2_ready_o),
+      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), 
.tx_f36_dst_rdy_o(rd2_ready_i) );
    
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile
index 4358d7c..e0a78bf 100644
--- a/usrp2/fpga/top/u2_rev3/Makefile
+++ b/usrp2/fpga/top/u2_rev3/Makefile
@@ -84,7 +84,12 @@ control_lib/wb_bridge_16_32.v \
 control_lib/reset_sync.v \
 control_lib/priority_enc.v \
 control_lib/pic.v \
+udp/udp_wrapper.v \
+udp/fifo19_rxrealign.v \
+udp/prot_eng_tx.v \
+udp/add_onescomp.v \
 simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac_wrapper19.v \
 simple_gemac/simple_gemac.v \
 simple_gemac/simple_gemac_wb.v \
 simple_gemac/simple_gemac_tx.v \
@@ -105,11 +110,15 @@ control_lib/newfifo/buffer_pool.v \
 control_lib/newfifo/fifo_2clock.v \
 control_lib/newfifo/fifo_2clock_cascade.v \
 control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
 control_lib/newfifo/fifo_short.v \
 control_lib/newfifo/fifo_long.v \
 control_lib/newfifo/fifo_cascade.v \
 control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo19_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo19.v \
+control_lib/newfifo/fifo36_to_fifo19.v \
+control_lib/newfifo/fifo19_to_fifo36.v \
 control_lib/longfifo.v \
 control_lib/shortfifo.v \
 control_lib/medfifo.v \
@@ -119,6 +128,8 @@ coregen/fifo_xlnx_512x36_2clk.v \
 coregen/fifo_xlnx_512x36_2clk.xco \
 coregen/fifo_xlnx_64x36_2clk.v \
 coregen/fifo_xlnx_64x36_2clk.xco \
+coregen/fifo_xlnx_16x19_2clk.v \
+coregen/fifo_xlnx_16x19_2clk.xco \
 extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
diff --git a/usrp2/fpga/udp/add_onescomp.v b/usrp2/fpga/udp/add_onescomp.v
new file mode 100644
index 0000000..048842a
--- /dev/null
+++ b/usrp2/fpga/udp/add_onescomp.v
@@ -0,0 +1,12 @@
+
+
+module add_onescomp
+  #(parameter WIDTH = 16)
+   (input [WIDTH-1:0] A,
+    input [WIDTH-1:0] B,
+    output [WIDTH-1:0] SUM);
+
+   wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
+   assign SUM  = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
+   
+endmodule // add_onescomp
diff --git a/usrp2/fpga/control_lib/newfifo/fifo19_rxrealign.v 
b/usrp2/fpga/udp/fifo19_rxrealign.v
similarity index 100%
rename from usrp2/fpga/control_lib/newfifo/fifo19_rxrealign.v
rename to usrp2/fpga/udp/fifo19_rxrealign.v
diff --git a/usrp2/fpga/udp/prot_eng_rx.v b/usrp2/fpga/udp/prot_eng_rx.v
new file mode 100644
index 0000000..5df158b
--- /dev/null
+++ b/usrp2/fpga/udp/prot_eng_rx.v
@@ -0,0 +1,121 @@
+
+
+
+// Protocol Engine Receiver
+//  Checks each line (16 bits) against values in setting regs
+//  3 options for each line -- 
+//      Error if mismatch, Slowpath if mismatch, or ignore line
+//  The engine increases the length of each packet by 32 or 48 bits,
+//   bringing the total length to a multiple of 32 bits.  The last line
+//   is entirely new, and contains the results of the matching operation:
+//      16 bits of flags, 16 bits of data.  Flags indicate error or slowpath
+//      Data indicates line that caused mismatch if any.
+
+
+//   Flags[2:0] is {occ, eop, sop}
+//   Protocol word format is:
+//             22   Last Header Line
+//             21   SLOWPATH if mismatch
+//             20   ERROR if mismatch
+//             19   This is the IP checksum
+//             18   This is the UDP checksum
+//             17   Compute IP checksum on this word
+//             16   Compute UDP checksum on this word
+//           15:0   data word to be matched
+
+module prot_eng_rx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   localparam HDR_WIDTH  = 16 + 7;  // 16 bits plus flags
+   localparam HDR_LEN   = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word  = header_ram[state];
+
+   wire consume_input  = src_rdy_i & dst_rdy_o;
+   wire produce_output         = src_rdy_o & dst_rdy_i;
+   
+   // Main State Machine
+   reg [15:0] pkt_length, fail_word, dataout_int;
+   
+   reg slowpath, error, sof_o, eof_o, occ_o, odd;
+
+   assign dataout    = {occ_o, eof_o, sof_o, dataout_int};
+
+   wire [15:0] calc_ip_checksum, calc_udp_checksum;
+   reg [15:0] rx_ip_checksum, rx_udp_checksum;
+
+   always @(posedge clk) 
+     if(header_word[19]) 
+       rx_ip_checksum  <= datain[15:0];
+   always @(posedge clk) 
+     if(header_word[18]) 
+       rx_udp_checksum <= datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+         slowpath     <= 0;
+         error        <= 0;
+         state        <= 0;
+         fail_word    <= 0;
+         eof_o        <= 0;
+         occ_o        <= 0;
+       end
+     else if(src_rdy_i & dst_rdy_i)
+       case (state)
+        0 :
+          begin
+             slowpath     <= 0;
+             error        <= 0;
+             eof_o        <= 0;
+             occ_o        <= 0;
+             state        <= 1;
+          end
+
+        ST_SLOWPATH :
+          ;
+        ST_ERROR :
+          ;
+        ST_PAYLOAD :
+          ;
+        ST_FILLER :
+          ;
+        ST_END1 :
+          ;
+        ST_END2 :
+          ;
+        default :
+          if(header_word[21] && mismatch)
+            state <= ST_SLOWPATH;
+          else if(header_word[20] && mismatch)
+            state <= ST_ERROR;
+          else if(header_word[22])
+            state <= ST_PAYLOAD;
+          else
+            state <= state + 1;
+       endcase // case (state)
+   
+
+
+   // IP + UDP checksum state machines
+   checksum_sm ip_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[17]), .clear(state==0), 
.checksum(ip_checksum));
+   
+   checksum_sm udp_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[16]), .clear(state==0), 
.checksum(udp_checksum));
+   
+endmodule // prot_eng_rx
diff --git a/usrp2/fpga/udp/prot_eng_tx.v b/usrp2/fpga/udp/prot_eng_tx.v
new file mode 100644
index 0000000..9031011
--- /dev/null
+++ b/usrp2/fpga/udp/prot_eng_tx.v
@@ -0,0 +1,119 @@
+
+// The input FIFO contents should be 16 bits wide
+//   The first word is 1 for fast path (accelerated protocol)
+//                     0 for software implemented protocol
+//   The second word is the number of bytes in the packet, 
+//         and must be valid even if we are in slow path mode
+//            Odd means the last word is half full
+//   Flags[1:0] is {eop, sop}
+//   Protocol word format is:
+//             19   Last Header Line
+//             18   IP Header Checksum XOR
+//             17   IP Length Here
+//             16   UDP Length Here
+//           15:0   data word to be sent
+
+module prot_eng_tx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   wire [2:0] flags_i = datain[18:16];
+   reg [15:0] dataout_int;
+   reg fast_path, sof_o;
+   
+   wire [2:0] flags_o   = {flags_i[2], flags_i[1], sof_o};  // OCC, EOF, SOF
+
+   assign dataout       = {flags_o[2:0], dataout_int[15:0]};
+
+   reg [4:0] state;
+   wire do_payload      = (state == 31);
+   
+   assign dst_rdy_o     = dst_rdy_i & (do_payload | (state==0) | (state==1) | 
(state==30));
+   assign src_rdy_o     = src_rdy_i & ~((state==0) | (state==1) | (state==30));
+   
+   localparam HDR_WIDTH  = 16 + 4;  // 16 bits plus flags
+   localparam HDR_LEN   = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word = header_ram[state];
+
+   wire last_hdr_line  = header_word[19];
+   wire ip_chk                = header_word[18];
+   wire ip_len                = header_word[17];
+   wire udp_len        = header_word[16];
+   
+   // Protocol State Machine
+   reg [15:0] length;
+   wire [15:0] ip_length = length + 28;  // IP HDR + UDP HDR
+   wire [15:0] udp_length = length + 8;  //  UDP HDR
+
+   always @(posedge clk)
+     if(reset)
+       begin
+         state     <= 0;
+         fast_path <= 0;
+         sof_o   <= 0;
+       end
+     else
+       if(src_rdy_i & dst_rdy_i)
+        case(state)
+          0 :
+            begin
+               fast_path <= datain[0];
+               state <= 1;
+            end
+          1 :
+            begin
+               length  <= datain[15:0];
+               sof_o <= 1;
+               if(fast_path)
+                 state <= 2;
+               else
+                 state <= 30;  // Skip 1 word for alignment
+            end
+          30 :
+            state <= 31;
+          31 :
+            begin
+               sof_o <= 0;
+               if(flags_i[1]) // eop
+                 state <= 0;
+            end
+          default :
+            begin
+               sof_o   <= 0;
+               if(~last_hdr_line)
+                 state <= state + 1;
+               else
+                 state <= 31;
+            end
+        endcase // case (state)
+
+   wire [15:0] checksum;
+   add_onescomp #(.WIDTH(16)) add_onescomp 
+     (.A(header_word[15:0]),.B(ip_length),.SUM(checksum));
+
+   always @*
+     if(ip_chk)
+       //dataout_int   <= header_word[15:0] ^ ip_length;
+       dataout_int     <= 16'hFFFF ^ checksum;
+     else if(ip_len)
+       dataout_int     <= ip_length;
+     else if(udp_len)
+       dataout_int     <= udp_length;
+     else if(do_payload)
+       dataout_int     <= datain[15:0];
+     else
+       dataout_int     <= header_word[15:0];
+   
+endmodule // prot_eng_tx
diff --git a/usrp2/fpga/udp/prot_eng_tx_tb.v b/usrp2/fpga/udp/prot_eng_tx_tb.v
new file mode 100644
index 0000000..e7ffeb5
--- /dev/null
+++ b/usrp2/fpga/udp/prot_eng_tx_tb.v
@@ -0,0 +1,167 @@
+module prot_eng_tx_tb();
+
+   localparam BASE = 128;
+   reg clk    = 0;
+   reg rst    = 1;
+   reg clear  = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data;
+   reg [1:0] f36_occ;
+   reg f36_sof, f36_eof;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   reg [15:0] count;
+
+   wire [35:0] casc_do;
+   wire [18:0] final_out, prot_out;
+
+   wire src_rdy_final, dst_rdy_final, src_rdy_prot;
+   reg dst_rdy_prot =0;
+   
+   wire dst_rdy_f36o ;
+   fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o));
+
+   fifo36_to_fifo19 fifo_converter
+     (.clk(clk),.reset(rst),.clear(clear),
+      
.f36_datain(casc_do),.f36_src_rdy_i(src_rdy_f36o),.f36_dst_rdy_o(dst_rdy_f36o),
+      
.f19_dataout(final_out),.f19_src_rdy_o(src_rdy_final),.f19_dst_rdy_i(dst_rdy_final));
+
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+       
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      
.datain(final_out[18:0]),.src_rdy_i(src_rdy_final),.dst_rdy_o(dst_rdy_final),
+      
.dataout(prot_out[18:0]),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot));
+   
+   reg [35:0] printer;
+
+   task WriteSREG;
+      input [7:0] addr;
+      input [31:0] data;
+
+      begin
+        @(posedge clk);
+        set_addr <= addr;
+        set_data <= data;
+        set_stb  <= 1;
+        @(posedge clk);
+        set_stb <= 0;
+      end
+   endtask // WriteSREG
+       
+   task ReadFromFIFO36;
+      begin
+        $display("Read from FIFO36");
+        #1 dst_rdy_prot <= 1;
+        while(~src_rdy_prot)
+          @(posedge clk);
+        while(1)
+          begin
+             while(~src_rdy_prot)
+               @(posedge clk);
+             $display("Read: %h",prot_out);
+             @(posedge clk);
+          end
+      end
+   endtask // ReadFromFIFO36
+   
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+        count        <= 4;
+        src_rdy_f36i <= 1;
+        f36_data     <= 32'h0001_000c;
+        f36_sof      <= 1;
+        f36_eof      <= 0;
+        f36_occ      <= 0;
+       
+        $display("Put Packet in FIFO36");
+        while(~dst_rdy_f36i)
+          @(posedge clk);
+        @(posedge clk);
+        $display("PPI_FIFO36: Entered First Line");
+        f36_sof  <= 0;
+        f36_data <= data_start;
+        while(~dst_rdy_f36i)
+          @(posedge clk);
+        @(posedge clk);
+        while(count+4 < data_len)
+          begin
+             f36_data <= f36_data + 32'h01010101;
+             count    <= count + 4;
+             while(~dst_rdy_f36i)
+               @(posedge clk);
+             @(posedge clk);
+             $display("PPI_FIFO36: Entered New Line");
+          end
+        f36_data  <= f36_data + 32'h01010101;
+        f36_eof   <= 1;
+        if(count + 4 == data_len)
+          f36_occ <= 0;
+        else if(count + 3 == data_len)
+          f36_occ <= 3;
+        else if(count + 2 == data_len)
+          f36_occ <= 2;
+        else
+          f36_occ <= 1;
+        while(~dst_rdy_f36i)
+          @(posedge clk);
+        @(posedge clk);
+        f36_occ      <= 0;
+        f36_eof      <= 0;
+        f36_data     <= 0;
+        src_rdy_f36i <= 0;
+        $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("prot_eng_tx_tb.vcd");
+   initial $dumpvars(0,prot_eng_tx_tb);
+
+   initial
+     begin
+       #10000;
+       @(posedge clk);
+       ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+       @(negedge rst);
+       @(posedge clk);
+       WriteSREG(BASE, {12'b0, 4'h0, 16'h0000});
+       WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000});
+       WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD});
+       WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234});
+       WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678});
+       WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD});
+       WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD});
+       WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD});
+       WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD});
+       WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD});
+       @(posedge clk);
+       PutPacketInFIFO36(32'hA0B0C0D0,16);
+       @(posedge clk);
+       @(posedge clk);
+       #10000;
+       @(posedge clk);
+       PutPacketInFIFO36(32'hE0F0A0B0,36);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // prot_eng_tx_tb
diff --git a/usrp2/fpga/udp/udp_wrapper.v b/usrp2/fpga/udp/udp_wrapper.v
new file mode 100644
index 0000000..490e392
--- /dev/null
+++ b/usrp2/fpga/udp/udp_wrapper.v
@@ -0,0 +1,78 @@
+
+module udp_wrapper
+  #(parameter BASE=0,
+    parameter RXFIFOSIZE=11)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o,
+    output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i,
+    
+    output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o
+    );
+   
+   wire         tx_int1_src_rdy, tx_int1_dst_rdy;
+   wire [18:0]          tx_int1_data;
+   
+   wire         tx_int2_src_rdy, tx_int2_dst_rdy;
+   wire [18:0]          tx_int2_data;
+   
+   // TX side
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_), 
.f36_dst_rdy_o(tx_f36_dst_rdy_o),
+      .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), 
.f19_dst_rdy_i(tx_int1_dst_rdy) );
+
+   fifo_short #(.WIDTH(19)) shortfifo19_a
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), 
.dst_rdy_o(tx_int1_dst_rdy),
+      .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), 
.dst_rdy_i(tx_int2_dst_rdy),
+      .space(), .occupied() );
+     
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), 
.dst_rdy_o(tx_int2_dst_rdy),
+      .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), 
.dst_rdy_i(tx_f19_dst_rdy_i) );
+
+   // RX side
+   wire rx_int1_src_rdy, rx_int1_dst_rdy;
+   wire [18:0] rx_int1_data;
+      
+   wire rx_int2_src_rdy, rx_int2_dst_rdy;
+   wire [18:0] rx_int2_data;
+      
+   wire rx_int3_src_rdy, rx_int3_dst_rdy;
+   wire [35:0] rx_int3_data;
+   
+`ifdef USE_PROT_ENG
+   prot_eng_rx #(.BASE(BASE)) prot_eng_rx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), 
.dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), 
.dst_rdy_i(rx_int1_dst_rdy) );
+`else
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), 
.dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), 
.dst_rdy_i(rx_int1_dst_rdy) );
+`endif // !`ifdef USE_PROT_ENG
+   
+   fifo_short #(.WIDTH(19)) shortfifo19_b
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), 
.dst_rdy_o(rx_int1_dst_rdy),
+      .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), 
.dst_rdy_i(rx_int2_dst_rdy),
+      .space(), .occupied() );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), 
.f19_dst_rdy_o(rx_int2_dst_rdy),
+      .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), 
.f36_dst_rdy_i(rx_int3_dst_rdy) );
+   
+   fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), 
.dst_rdy_o(rx_int3_dst_rdy),
+      .dataout({f36_flags_o,f36_data_o}), .src_rdy_o(f36_src_rdy_o), 
.dst_rdy_i(f36_dst_rdy_i),
+      .space(), .occupied() );
+
+   
+endmodule // udp_wrapper