[Commit-gnuradio] [gnuradio] 134/148: remove time_sync and master_timer.

[git]

This is an automated email from the git hooks/post-receive script.

nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.

commit 8323aa565e9f5a7bfcb1f1483a90b5d63688e842
Author: Matt Ettus <address@hidden>
Date:   Mon Jan 18 17:56:55 2010 -0800

    remove time_sync and master_timer.
    
    Master timer replaced with simple_timer which needs new memory map and 
control
    functions.  it allows onetime and periodic interrupts.  Copied from 
quad_radio
    
    time_sync functionality will go in time_64bit.  Right now it only does
    external SMA connector, not mimo connector
---
 usrp2/fpga/timing/simple_timer.v | 60 ++++++++++++++++++++++++++++++++++++++++
 usrp2/fpga/top/u2_core/u2_core.v | 41 +++++++++++++--------------
 usrp2/fpga/top/u2_rev3/Makefile  |  3 +-
 3 files changed, 82 insertions(+), 22 deletions(-)

diff --git a/usrp2/fpga/timing/simple_timer.v b/usrp2/fpga/timing/simple_timer.v
new file mode 100644
index 0000000..17c7f1c
--- /dev/null
+++ b/usrp2/fpga/timing/simple_timer.v
@@ -0,0 +1,60 @@
+
+
+module simple_timer
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output reg onetime_int, output reg periodic_int);
+
+   reg [31:0]  onetime_ctr;
+   always @(posedge clk)
+     if(reset)
+       begin
+         onetime_int     <= 0;
+         onetime_ctr     <= 0;
+       end
+     else
+       if(set_stb & (set_addr == BASE))
+        begin
+           onetime_int   <= 0;
+           onetime_ctr   <= set_data;
+        end
+       else 
+        begin
+           if(onetime_ctr == 1)
+             onetime_int <= 1;
+           if(onetime_ctr != 0)
+             onetime_ctr <= onetime_ctr - 1;
+           else
+             onetime_int <= 0;
+        end // else: !if(set_stb & (set_addr == BASE))
+   
+   reg [31:0]  periodic_ctr, period;
+   always @(posedge clk)
+     if(reset)
+       begin
+         periodic_int       <= 0;
+         periodic_ctr       <= 0;
+         period             <= 0;
+       end
+     else
+       if(set_stb & (set_addr == (BASE+1)))
+        begin
+           periodic_int     <= 0;
+           periodic_ctr     <= set_data;
+           period           <= set_data;
+        end
+       else 
+        if(periodic_ctr == 1)
+          begin
+             periodic_int   <= 1;
+             periodic_ctr   <= period;
+          end
+        else
+          if(periodic_ctr != 0)
+            begin
+               periodic_int <= 0;
+               periodic_ctr <= periodic_ctr - 1;
+            end
+   
+endmodule // simple_timer
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index 8cd150c..e384e2b 100644
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -141,6 +141,7 @@ module u2_core
    localparam SR_TX_DSP = 208;
    localparam SR_TX_CTRL = 224;
    localparam SR_TIME64 = 192;
+   localparam SR_SIMTIMER = 198;
    
    wire [7:0]  set_addr;
    wire [31:0]         set_data;
@@ -150,7 +151,8 @@ module u2_core
    wire        ram_loader_rst, wb_rst, dsp_rst;
 
    wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
-   wire        bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, 
proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+   wire        bus_error, spi_int, i2c_int, pps_int, onetime_int, 
periodic_int, buffer_int;
+   wire        proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
 
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
@@ -481,8 +483,8 @@ module u2_core
 
    assign irq= {{8'b0},
                {8'b0},
-               {4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
-               
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+               {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, 
uart_rx_int},
+               
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
    
    pic 
pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
           
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
@@ -491,13 +493,25 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Master Timer, Slave #9
 
+   // No longer used, replaced with simple_timer below
+   /*
    wire [31:0]          master_time;
    timer timer
      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
       .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
       .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
-
+    */
+   assign s9_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   //  Simple Timer interrupts
+   
+   simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .onetime_int(onetime_int), .periodic_int(periodic_int));
+   
    // /////////////////////////////////////////////////////////////////////////
    // UART, Slave #10
 
@@ -525,22 +539,9 @@ module u2_core
    // 
//////////////////////////////////////////////////////////////////////////
    // Time Sync, Slave #12 
 
-   reg                  pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
-   always @(negedge dsp_clk) pps_negedge <= pps_in;
-   always @(posedge dsp_clk) pps_posedge <= pps_in;
-   always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
-   always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;   
+   // No longer used, see time_64bit.  Still need to handle mimo time, though
+   assign sc_ack = 0;
    
-   wire         pps_o;
-   time_sync time_sync
-     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
-      .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
-      .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
-      .sys_clk_i(dsp_clk),.master_time_o(master_time),
-      .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
-      .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
-      .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
-
    // /////////////////////////////////////////////////////////////////////////
    // SD Card Reader / Writer, Slave #13
 
@@ -678,7 +679,7 @@ module u2_core
 
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), 
.set_data(set_data),
-      .pps(pps_o), .vita_time(vita_time), .pps_int());
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
    
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile
index 1f8bbe3..57d5510 100644
--- a/usrp2/fpga/top/u2_rev3/Makefile
+++ b/usrp2/fpga/top/u2_rev3/Makefile
@@ -179,8 +179,7 @@ timing/time_64bit.v \
 timing/time_compare.v \
 timing/time_receiver.v \
 timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
+timing/simple_timer.v \
 top/u2_core/u2_core.v \
 top/u2_rev3/u2_rev3.ucf \
 top/u2_rev3/u2_rev3.v