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Re: [Help-gnucap] modelling digital control of PWM circuits
From: |
al davis |
Subject: |
Re: [Help-gnucap] modelling digital control of PWM circuits |
Date: |
Sat, 5 Mar 2011 14:10:57 -0500 |
User-agent: |
KMail/1.13.5 (Linux/2.6.32-trunk-amd64; KDE/4.4.5; x86_64; ; ) |
On Tuesday 01 March 2011, John Vodden wrote:
> I am trying to find out if gnucap's mixed-mode capabilities
> are suitable for my purposes. Basically, I am trying to
> model digital control of PWM inverter/rectifier circuits
> using ideal switches. I understand that gnucap models
> switches as "time-dependant linear devices" and adjusts the
> simulation timing accordingly.
Should be. If not, how about helping to add the capability?
> Is it possible to write an external model that can set when
> the switches will operate? Ideally, this model would be
> triggered at regular intervals (rather like a timed
> interrupt) and perform calculations based on current or
> voltage measurements to determine the instant at which the
> switches should change state and somehow schedule the change
> of state to take place (perhaps adjusting the control
> voltage of a voltage dependant switch?)
Yes, but how about a switch and a timed voltage source? Both of
these are available now.
> I have read about the model compiler in the stable version of
> gnucap but I get the impression that this is somewhat
> obsolete? I also think that the development version is more
> sophisticated than the stable release but I am struggling to
> find documentation. I would greatly appreciate it if someone
> could point me in the right direction of where to start with
> this, or alternatively send me on my way if this is not
> something that gnucap is able to do.
Documentation for the development version is a wiki ..
http://gnucap.org/dokuwiki/doku.php?id=gnucap:manual
Technical documentation is at:
http://gnucap.org/dokuwiki/doku.php?id=gnucap:manual:tech
What is obsolete is the source language. Modelgen was done long
ago, before Verilog-A.
It needs to accept Verilog-A as the source language. There are
several possible approaches. One possible approach is to change
modelgen to accept Verilog-A syntax. Other thoughts are to base
a replacement on ADMS, Icarus Verilog, or System-C. There have
been starts on all of these, but since nobody is getting paid,
none of these were finished.