Re: GNU Make Question about string replace in dependency list

[Philip Guenther]

address@hidden (DeMarco, Paul) writes:
>I am having trouble with my makefile rebuilding cpp files when it shouldn't
> 
>I absolutly could not get separate directory compilation working:
>be in the object dir with source in another dir, it's for cross
>platform dev.
> 
>So I fell back to old faithful:
>node.o: $(SRC)/node.cpp $(INCL)/node.h
>    $(CC) $(CPPFLAGS) $(SRC)/node.cpp
> 
>but I realized that there would be a lot of maintenance since I
>couldn't get the suffix rules to work properly I decided to save
>myself some work by using this:
> 
>node.o: $(SRC)/$(@:.o=.cpp) $(INCL)/$(@:.cpp=.h)
> $(CC) $(CPPFLAGS) $(SRC)/$(@:.o=.cpp)
>
>Unfortunatly it rebuilds way too often when it shouldn't.  Is this
>an acceptable method of constructing a dependancy list?

Nope.  The dependency list is expanded when the rule is encountered,
so automatic variables are not set at that time.  (There's an
exception, but you didn't hit it.)  The 'right' way to do this is
with a pattern rule, or a static pattern rule.  If the same pattern
and command apply to all the .o files, then this works:

%.o: $(SRC)/%.cpp $(INCL)/%.h
        $(CC) $(CPPFLAGS) -o $@ $(SRC)/$(@:.o=.cpp)


If different sets of files need different 'mappings' from source
path to object, then a static pattern rule will do the trick:

CPP_OBJ = node.o foo.o

$(CPP_OBJ): %.o: $(SRC)/%.cpp $(INCL)/%.h
        $(CC) $(CPPFLAGS) -o $@ $(SRC)/$(@:.o=.cpp)

C_OBJ = low_level.o

$(C_OBJ): %.o: $(SRC)/%.c $(INCL)/%.h
        $(CC) $(CPPFLAGS) -o $@ $(SRC)/$(@:.o=.c)


Philip Guenther