Loops in makefile

[dsudha]

Hello all 

I have a variable from which my target names are derived, for example 

listvar = a b c p l w q x y 

The targets are made as follows 

apnd.t : apnd.s a.h
bpnd.t : bpnd.s b.h
.
.
xpnd.t : xpnd.s x.h
ypnd.t : ypnd.s y.h 


Is there any way I can loop through $(listvar) in the makefile instead of 
explicitly writing them all out? 

Thanks
DS