Re: Loops in makefile

[Boris Kolpackov]

address@hidden writes:

> I have a variable from which my target names are derived, for example 
> 
> listvar = a b c p l w q x y 
> 
> The targets are made as follows 
> 
> apnd.t : apnd.s a.h
> bpnd.t : bpnd.s b.h
> .
> .
> xpnd.t : xpnd.s x.h
> ypnd.t : ypnd.s y.h 
> 
> 
> Is there any way I can loop through $(listvar) in the makefile instead of 
> explicitly writing them all out? 

How about something like this:

listvar := a b c

.PHONY: all
all : $(listvar)

define Rule
.PHONY: a
$(1):; @echo $$@
endef

$(foreach target,$(listvar),$(eval $(call Rule,$(target))))

Also you may want to look at the documentation of $(foreach ), $(call ) and
$(eval).

hth,
-boris