Re: static pattern variables, bug or feature ?

[Benoit Poulot-Cazajous]

Greg Chicares <address@hidden> writes:

> Benoit Poulot-Cazajous wrote:
> > 
> > Consider this Makefile :
> > 
> > toto: toto.o
> > toto: CFLAGS=-g
> > %.o: %.c
> >         gcc -o $@ -c $< $(CFLAGS)
> > %: %.o
> >         gcc -o $@ $<
> > 
> [move example below for discussion]
> > So, it looks like variable definitions in static patterns can "propagate"
> > to dependencies. While it can be useful, it is also quite confusing.
> > Is it a bug, that may be fixed one day, or a feature that we can rely on ?

> The "Target-specific Variable Values" section of the make manual
> discusses this. As I read it, it says this is a feature:
>   "when you define a target-specific variable, that variable value
>   is also in effect for all prerequisites of this target"
>... 
> > but 'make toto.o toto' gives :
> >         gcc -o toto.o -c toto.c
> >         gcc -o toto toto.o
> 
> Target 'toto.o' is made, with no particular $(CFLAGS).

Why ? 
My understanding is that 'toto: toto.o'
means 'toto.o is a prerequisite of toto', so, according to
the manual, CFLAGS should be in effect for toto.o.
It clearly isn't, so maybe the documentation should read :

        when you define a target-specific variable, that
        variable value is also in effect for all prerequisites
        of this target _when it is processed_

   -- Benoit