simply expanded variable getting overwritten

[micron_make]

Hi,
I have one main makefile which includes two sub-makefiles residing in two
different directories.
 I have the following lines in my main make file

EXP_MOD_NAM:=one
include Module/$(EXP_MOD_NAM)/gen.mak

EXP_MOD_NAM:=two
include Module/$(EXP_MOD_NAM)/gen.mak

In both the sub-make files(gen.mak) I have the following same lines
(stripped down)
#to get all the c files
$(EXP_MOD_NAM)_NAM := $(wildcard Module/$(EXP_MOD_NAM)/*.c)
#to store "this" Module name
local_mod:= $(EXP_MOD_NAM)
#gloablly update files to build
FILES_TO_BUILD += $($(EXP_MOD_NAM)_NAM)

#below line will be  actually $(RM) Module/$(loc_mod)/*.bak in production
code 
CLCMD:=  Module/$(loc_mod)/*.bak

$(loc_mod)_clean: 
        @echo $(CLCMD) 

When I run 
>make one_clean 
I get Module/two/*.bak i.e. loc_mod is two  and not one. Since loc_mode is
simply expanded variable my thought was loc_mod should be one.As I see the
target expands to one_clean correctly but no the variable in the command. Is
this right behaviour? Is there a way to preserve the variable value
"locally"?

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