RE: simply expanded variable getting overwritten

[micron_make]

Hi,
>You don't need eval for this.  There are a number of ways to do it.  A
>more-or-less portable way (works with all versions of GNU make and many
>other versions of make, but not all), would be to use automatic
>variables:

       $(loc_mod)_CLCMD := Module/$(loc_mod)/*.bak
        
        $(loc_mod)_clean:
                @echo $($(@:_clean=)_CLCMD)
This worked for me. It was difficult to find any specific documentation  for
this kind (($(@: )of usage of automatic variables in the GNU Make pdf. Could
you please point me to some documentation stressing on usage with some
examples.

>Another, slightly fancier option would be to use target-specific
>variables:

        $(loc_mod)_clean: CLCMD := Module/$(loc_mod)/*.bak
        $(loc_mod)_clean:
                @echo $(CLCMD)
This method also worked for me. And after reading the chapter about target
specific variables, I guess this is what I would like to use.
Thanks a lot for the inputs.

I couldn't get  eval method working
> To get it expanded earlier, you need an eval:
> 
> define clean_rule
> $(loc_mod)_clean:
>         @echo $$($(loc_mod)_CLCMD)
> endef
> 
> $(eval $(call clean_rule))

I get "prerequisites cannot be defined in command scripts. Stop"

The way I am using eval is
define clean_rule
 $(loc_mod)_clean:
         @echo $$($(loc_mod)_CLCMD)
 endef
 
$(loc_mod)_clean:
    $(eval $(call clean_rule))

And fromthe command line I run 
>make one_clean

Am I doing something wrong here? Just curious to know since I want to
explore the eval function in detail.

Cheers!!

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