Re: Different compilation based on filename

[CHEN Cheng]

On Sat, Sep 12, 2009 at 06:32:51PM -0400, Paul Smith wrote:
[...]
> Another is constructed variable names.  Variable names in make can
> consist of other variables.  So you could do something like this:
> 
>       foo.o_CFLAGS = -g
> 
>       %.o : %.c
>               $(CC) $(CFLAGS) $(address@hidden) -o $@ -c $<
> 
> The $(address@hidden) (or, equivalently, $($(@)_CFLAGS)) expands to the value
> contained in the variable named by concatenating the target ($@) with
> the string _CFLAGS.
> 
> Personally I find this method the most aesthetically pleasing, mainly
> because in my complex make environments I like to have all the "user
> visible" makefile purely data-driven: they simply declare variables but
> never need to declare rules.  The rules are all created in some deeply
> magical common makefiles set up for the project.

Beautiful. It reminds me the Automake style and the Linux kernel Kbuild,
while the Kbuild also put variable (non-automatic) into variable names.

Thanks, Paul, for the nice articles, including the jobserver description.


Best,
Cheng