Re: eval of foreach loop of a define runs first target more than once

[Philip Guenther]

On Fri, May 21, 2010 at 10:06 AM, Utku Ozcan <address@hidden> wrote:
> In following Makefile, "gmake" returns me always the message
>
> unix> gmake
> gmake: `codefile_list_CODE' is up to date.

You might also notice that if you run "gmake -n" it *still* creates the files!


> .. as though the target generated for first member of the list
> CODE_SRCS_LIST is executed twice.
> I see the files are generated correctly, but "make" tries to generate
> the first file 2nd time.
>
> However the define "write_list_to_file" is has following code,
>
> define write_list_to_file
> $(2):
>        printf "$(1)\n"
> endef
>
> ... ie, no $(foreach) code, the output is
>
> printf "CODE_SRCS\n" codefile_list_CODE_part01:
> CODE_SRCS
> printf "CODE_part01_SRCS\n" codefile_list_CODE_part02:
> CODE_part01_SRCS
> printf "CODE_part02_SRCS\n" codefile_list_CODE_part03:
> CODE_part02_SRCS
> printf "CODE_part03_SRCS\n"
> CODE_part03_SRCS
>
> I had expected that first iteration must be done again, like above,
> however it isn't.
>
> Shall I ignore "up to date" message in the original code?
> If not, where is my mistake?
>
> Why is the call behaviour different in both defines?
>
> #### Makefile ####
> CODE_SRCS_LIST := \
>  CODE \
>  CODE_part01 \
>  CODE_part02 \
>  CODE_part03
>
> CODE_SRCS :=
> CODE_SRCS += a
> CODE_SRCS += b
>
> CODE_part01_SRCS :=
> CODE_part01_SRCS += c
> CODE_part01_SRCS += d
>
> CODE_part02_SRCS :=
> CODE_part02_SRCS += e
> CODE_part02_SRCS += f
>
> CODE_part03_SRCS :=
> CODE_part03_SRCS += g
> CODE_part03_SRCS += h
>
> define write_list_to_file
> $(2):
>   $(foreach file,$($1),$(shell echo $(file) >> $(2)))
> endef

As you noticed, this function is completely broken.  Consider the
output and side-effects of

$(info $(call write_list_to_file foo,bar))

Note that simply putting that line in the makefiles results in the
creation of the file 'bar' EVEN IF 'bar' ISN'T A MAKE TARGET!  When
does the $(shell) function get expanded?

Why are you using the make functions $(foreach) and $(shell) in the
commands for the rule and not just writing shell commands?  Did you
first write a correct Makefile that does stuff directly without using
$(eval) and only factor out the code after doing that?  If not, how
did you know what the generated Makefile rules should look like?


Philip Guenther