Re: How to expand computed variable names within for script command?

[Larry Evans]

On 07/27/2015 12:59 PM, Paul Smith wrote:
> On Mon, 2015-07-27 at 12:47 -0500, Larry Evans wrote:
>> How should the which command within the for loop script be
>> modified to produce the same output as the which command
>> before the for loop script?
> 
> The recipe is run by the shell, not by make.  Make simply expands the
> make variables and functions one time before the shell is started, then
> sends the results to the shell to be run, then waits for the exit code
> to see if it worked.  The shell, being a separate shell process, cannot
> access make's database of variables.  So, you cannot write a _shell_
> loop that uses _make_ computed variables.
> 
> If you want to use make variables, you have to use a make loop via
> $(foreach ...) or similar.
> 
> compiles:
>         make -version
>         @echo "COMPILE.gcc=" $(COMPILE.gcc)
>         which $(COMPILE.gcc)
>         for HOW_CXX in $(foreach C,gcc,$(COMPILE.$C)) ; do \
>           which $$HOW_CXX ; \
>         done ;
> 
Thanks Paul.  It works; however, what I really
want is to use the compiler to compile a source file to
and object file.

When I tried to modify the Makefile as shown in 1st attachment,
I get the output shown in 2nd attachment.  Apparently, it's
not globbing the gcc and the -c together.  Instead, it's using
gcc to produce the a.out file, which is not what I want and
during the 2nd loop, it's trying to use -c is a shell command.

How should I modify this 2nd version of the Makefile to make it compile
to produce the .o and not the a.out file?  BTW, I'd rather not
hardcode the -c into compile command because the actual args to the
compile command depend on the compiler.  Also, I'd like the output
object file name to be $(MAIN).gcc.o instead of just $(MAIN).o.

TIA.

-Larry

Makefile
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Makefile.out
Description: Text document