Simulating $(MAKE) FOO=bar without forking make?

[Sébastien Hinderer]

Dear all,

I am working on the build system of a boostrapping compiler.
The current design is that the root makefile calls sub-makefiles in the
different subdirectories of the project and I am trying to change
this so that the sub-makefiles get included into the main Makefile
rather than called, for the well-known reasons.

I have started to work on this, subdirectory by subdirectory, but
I find it to be not such a trivial task.

One of the things I do not really know how to deal with is that the main
Makefile sometimes does things like
ratget1:
         $(MAKE) -C dir FOO=bar

...

target2:
        $(MAKE) -C dir FOO=baz

This is used, e.g., to specify which compiler to use to compile the
files in dir and one really wants to be able to compile them with two
compilers, for instance to make sure the bootstrapped compiler works.

So my two questions are:

1. Is there a known / recommended way to simulate this in the context
of one makefile including other makefiles?

2. Are there projects such as a bootstrapping compiler where it is
really considered better practice to call sub-makefiles rather than
including them?

Many thanks in advance for any help,

Sébastien.