Re: Flag --no-builtin-rules etc. just for this makefile (no flag inheritance)

[Kaz Kylheku (gmake)]

On 2020-04-20 09:18, R. Diez wrote:
> > It can be verified with a minimal Makefile that "make 
> > --print-data-base"
> > shows an absence of built-in rules if MAKEFLAGS += --no-builtin-rules 
> > is
> > present, and likewise that --no-builtin-variables causes the variables
> > to disappear.
> > [...]
>
> Well, let's verify it then:
>
> Contents of file "makefile":
>
>   MAKEFLAGS += --no-builtin-variables
>
>   $(info CC: $(CC))
>
> Commands I used to test this scenario:
>
>   $ make --version
>   GNU Make 4.3
>   Built for x86_64-pc-linux-gnu
>
>   $ echo "The value of CC is: $CC"
>   The value of CC is:
>
>   $ make --file makefile
>   CC: cc
>   make: *** No targets. Stop.
>
>   $ make --file makefile  --no-builtin-variables
>   CC:
>   make: *** No targets. Stop.
>
> So it looks like "MAKEFLAGS += --no-builtin-variables" is not working,  
> is it?

I see that in spite of the variables being scrubbedd from the 
--print-data-base
view, $(CC) continues to evaluate to cc at the top-level.

This can be seen in the same invocation:

  $ cat mkfile
  MAKEFLAGS += --no-builtin-variables

  $(info CC is defined as: $(CC))


Test:

  $ make --print-data-base -f mkfile | grep CC
  make: *** No targets.  Stop.
  CC is defined as: cc

Now True Scotsman's brand industrial-strength no-builtin-variables:

  $ make --print-data-base --no-builtin-variables -f mkfile | grep CC
  make: *** No targets.  Stop.
  CC is defined as:

I think this has to do with the order of expansions. When the Makefile
is being read, CC is still defined, and so $(CC) expands. Then before
GNU Make actually starts processing the rule base, at that time it
honors the requests that have appeared in MAKEFLAGS.

In other words, it doesn't instantaneously react to the MAKEFLAGS += 
update.

If we change the makefile to this:

  MAKEFLAGS += --no-builtin-variables --no-builtin-rules

  $(info CC is defined as: $(CC))

  .PHONY: all
  all:
        echo [in rule] CC is defined as: $(CC)

Then:

  $ make -f  mkfile
  CC is defined as: cc
  echo [in rule] CC is defined as:
  [in rule] CC is defined as:

This means we can rely on --no-builtin-variables in MAKEFLAGS to work as 
long
as we avoid top-level capture via the := operator.

  MAKEFLAGS += --no-builtin-variables --no-builtin-rules

  HARD_CAPTURE_CC := $(CC)

  SOFT_CAPTURE_CC = $(CC)

  $(info CC is defined as: $(CC))

  .PHONY: all
  all:
        @echo [in rule] CC is defined as: $(CC)
        @echo [in rule] SOFT_CAPTURE_CC is defined as: $(SOFT_CAPTURE_CC)
        @echo [in rule] HARD_CAPTURE_CC is defined as: $(HARD_CAPTURE_CC)

Run:

  $ make -f  mkfile
  CC is defined as: cc
  [in rule] CC is defined as:
  [in rule] SOFT_CAPTURE_CC is defined as:
  [in rule] HARD_CAPTURE_CC is defined as: cc



Incidentally, what does POSIX have to say about this? POSIX defines 
MAKEFLAGS
and specifies its semantics as an environment variable being defined 
before
make executes.  And it says this: "The result of setting MAKEFLAGS in 
the
Makefile is unspecified."

https://pubs.opengroup.org/onlinepubs/9699919799/utilities/make.html