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[PATCH v5 12/22] target/arm: Implement the STGP instruction
From: |
Richard Henderson |
Subject: |
[PATCH v5 12/22] target/arm: Implement the STGP instruction |
Date: |
Fri, 11 Oct 2019 09:47:34 -0400 |
Signed-off-by: Richard Henderson <address@hidden>
---
v3: Handle atomicity, require pre-cleaned address.
---
target/arm/translate-a64.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c17b36ebb2..4ecb0a2fb7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2657,7 +2657,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
* +-----+-------+---+---+-------+---+-------+-------+------+------+
*
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
- * LDPSW 01
+ * LDPSW/STGP 01
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
* V: 0 -> GPR, 1 -> Vector
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
@@ -2682,6 +2682,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
bool is_signed = false;
bool postindex = false;
bool wback = false;
+ bool set_tag = false;
TCGv_i64 clean_addr, dirty_addr;
@@ -2694,6 +2695,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
if (is_vector) {
size = 2 + opc;
+ } else if (opc == 1 && !is_load) {
+ /* STGP */
+ if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) {
+ unallocated_encoding(s);
+ return;
+ }
+ size = 3;
+ set_tag = true;
} else {
size = 2 + extract32(opc, 1, 1);
is_signed = extract32(opc, 0, 1);
@@ -2746,6 +2755,15 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
}
clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31);
+ if (set_tag) {
+ TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
+ gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rn);
+ } else {
+ gen_helper_stg(cpu_env, clean_addr, tcg_rn);
+ }
+ }
+
if (is_vector) {
if (is_load) {
do_fp_ld(s, rt, clean_addr, size);
--
2.17.1
- [PATCH v5 01/22] target/arm: Add MTE_ACTIVE to tb_flags, (continued)
- [PATCH v5 01/22] target/arm: Add MTE_ACTIVE to tb_flags, Richard Henderson, 2019/10/11
- [PATCH v5 02/22] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/10/11
- [PATCH v5 03/22] target/arm: Add MTE system registers, Richard Henderson, 2019/10/11
- [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3}, Richard Henderson, 2019/10/11
- [PATCH v5 05/22] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/10/11
- [PATCH v5 06/22] target/arm: Implement the IRG instruction, Richard Henderson, 2019/10/11
- [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions, Richard Henderson, 2019/10/11
- [PATCH v5 08/22] target/arm: Implement the GMI instruction, Richard Henderson, 2019/10/11
- [PATCH v5 09/22] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/10/11
- [PATCH v5 12/22] target/arm: Implement the STGP instruction,
Richard Henderson <=
- [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/10/11
- [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/10/11
- [PATCH v5 14/22] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/10/11
- [PATCH v5 16/22] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/10/11
- [PATCH v5 15/22] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/10/11
- [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/10/11
- [PATCH v5 18/22] target/arm: Enable MTE, Richard Henderson, 2019/10/11
- [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2019/10/11
- [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/10/11
- [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/10/11