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[PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAtt
From: |
Richard Henderson |
Subject: |
[PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs |
Date: |
Fri, 11 Oct 2019 09:47:41 -0400 |
This "bit" is a particular value of the page's MemAttr.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e988398fce..17981d7c48 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9609,6 +9609,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
+ uint8_t memattr;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -9836,17 +9837,21 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
txattrs->target_tlb_bit0 = true;
}
+ if (mmu_idx == ARMMMUIdx_S2NS) {
+ memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4));
+ } else {
+ /* Index into MAIR registers for cache attributes */
+ uint64_t mair = env->cp15.mair_el[el];
+ memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8);
+ }
+
+ /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */
+ if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) {
+ txattrs->target_tlb_bit1 = true;
+ }
+
if (cacheattrs != NULL) {
- if (mmu_idx == ARMMMUIdx_S2NS) {
- cacheattrs->attrs = convert_stage2_attrs(env,
- extract32(attrs, 0, 4));
- } else {
- /* Index into MAIR registers for cache attributes */
- uint8_t attrindx = extract32(attrs, 0, 3);
- uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
- assert(attrindx <= 7);
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
- }
+ cacheattrs->attrs = memattr;
cacheattrs->shareability = extract32(attrs, 6, 2);
}
--
2.17.1
- [PATCH v5 09/22] target/arm: Implement the SUBP instruction, (continued)
- [PATCH v5 09/22] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/10/11
- [PATCH v5 12/22] target/arm: Implement the STGP instruction, Richard Henderson, 2019/10/11
- [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/10/11
- [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/10/11
- [PATCH v5 14/22] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/10/11
- [PATCH v5 16/22] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/10/11
- [PATCH v5 15/22] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/10/11
- [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/10/11
- [PATCH v5 18/22] target/arm: Enable MTE, Richard Henderson, 2019/10/11
- [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs,
Richard Henderson <=
- [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/10/11
- [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/10/11
- [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory, Richard Henderson, 2019/10/11
- Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, no-reply, 2019/10/11
- Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, Evgenii Stepanov, 2019/10/15