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Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode
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Subject: |
Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode |
Date: |
Fri, 11 Oct 2019 12:32:56 -0700 (PDT) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: address@hidden
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
2cb4ac6 target/arm: Add allocation tag storage for system mode
04c91b4 target/arm: Add mmu indexes for tag memory
1e0ff9d target/arm: Create tagged ram when MTE is enabled
b751fc4 target/arm: Cache the Tagged bit for a page in MemTxAttrs
9ac60fd target/arm: Enable MTE
513b429 target/arm: Set PSTATE.TCO on exception entry
b34fae3 target/arm: Implement data cache set allocation tags
e821379 target/arm: Clean address for DC ZVA
aff90e1 target/arm: Implement the access tag cache flushes
0caee2b target/arm: Implement the LDGM and STGM instructions
2b4a576 target/arm: Implement the STGP instruction
8dc4ae2 target/arm: Implement LDG, STG, ST2G instructions
2f4a984 target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY
3af0a57 target/arm: Implement the SUBP instruction
b26b9b0 target/arm: Implement the GMI instruction
83744f3 target/arm: Implement ADDG, SUBG instructions
454811d target/arm: Implement the IRG instruction
3570a15 target/arm: Suppress tag check for sp+offset
1409fa4 target/arm: Add helper_mte_check{1,2,3}
bbbd12d target/arm: Add MTE system registers
bac1b74 target/arm: Add regime_has_2_ranges
498eda0 target/arm: Add MTE_ACTIVE to tb_flags
=== OUTPUT BEGIN ===
1/22 Checking commit 498eda06038b (target/arm: Add MTE_ACTIVE to tb_flags)
ERROR: spaces prohibited around that ':' (ctx:WxW)
#214: FILE: target/arm/internals.h:986:
+ bool tcma : 1;
^
total: 1 errors, 0 warnings, 213 lines checked
Patch 1/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/22 Checking commit bac1b74f8ee9 (target/arm: Add regime_has_2_ranges)
3/22 Checking commit bbbd12d06479 (target/arm: Add MTE system registers)
4/22 Checking commit 1409fa4954ca (target/arm: Add helper_mte_check{1,2,3})
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 4/22 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/22 Checking commit 3570a158fe8a (target/arm: Suppress tag check for sp+offset)
6/22 Checking commit 454811d5fbee (target/arm: Implement the IRG instruction)
7/22 Checking commit 83744f3effbf (target/arm: Implement ADDG, SUBG
instructions)
8/22 Checking commit b26b9b0ff90d (target/arm: Implement the GMI instruction)
9/22 Checking commit 3af0a5757328 (target/arm: Implement the SUBP instruction)
10/22 Checking commit 2f4a98446331 (target/arm: Define
arm_cpu_do_unaligned_access for CONFIG_USER_ONLY)
11/22 Checking commit 8dc4ae2e080d (target/arm: Implement LDG, STG, ST2G
instructions)
12/22 Checking commit 2b4a576928a6 (target/arm: Implement the STGP instruction)
13/22 Checking commit 0caee2b19728 (target/arm: Implement the LDGM and STGM
instructions)
14/22 Checking commit aff90e1ac887 (target/arm: Implement the access tag cache
flushes)
15/22 Checking commit e82137999567 (target/arm: Clean address for DC ZVA)
16/22 Checking commit b34fae36a523 (target/arm: Implement data cache set
allocation tags)
17/22 Checking commit 513b42914b4f (target/arm: Set PSTATE.TCO on exception
entry)
18/22 Checking commit 9ac60fd7222d (target/arm: Enable MTE)
19/22 Checking commit b751fc4415fe (target/arm: Cache the Tagged bit for a page
in MemTxAttrs)
20/22 Checking commit 1e0ff9daa24d (target/arm: Create tagged ram when MTE is
enabled)
21/22 Checking commit 04c91b4cfe18 (target/arm: Add mmu indexes for tag memory)
22/22 Checking commit 2cb4ac638a77 (target/arm: Add allocation tag storage for
system mode)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to address@hidden
- [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions, (continued)
- [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/10/11
- [PATCH v5 14/22] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/10/11
- [PATCH v5 16/22] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/10/11
- [PATCH v5 15/22] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/10/11
- [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/10/11
- [PATCH v5 18/22] target/arm: Enable MTE, Richard Henderson, 2019/10/11
- [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2019/10/11
- [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/10/11
- [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/10/11
- [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory, Richard Henderson, 2019/10/11
- Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode,
no-reply <=
- Re: [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode, Evgenii Stepanov, 2019/10/15