[Qemu-commits] [qemu/qemu] b06901: hw/char/sifive_uart: Fix broken UART on big endian...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: b069018e2fe1fc613f5eeecc810050210e845528
      
https://github.com/qemu/qemu/commit/b069018e2fe1fc613f5eeecc810050210e845528
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M hw/char/sifive_uart.c

  Log Message:
  -----------
  hw/char/sifive_uart: Fix broken UART on big endian hosts

Casting a "uint32_t *" to a "uint8_t *" to get to the lowest 8-bit
part of the value does not work on big endian hosts. We've got to
take the proper detour through an 8-bit variable.

Fixes: 53c1557b23 ("hw/char: sifive_uart: Print uart characters async")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20241104163504.305955-1-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cd5d265f42fbb1d29cbc9d8805821149101c1d23
      
https://github.com/qemu/qemu/commit/cd5d265f42fbb1d29cbc9d8805821149101c1d23
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M hw/riscv/riscv-iommu.c

  Log Message:
  -----------
  hw/riscv/riscv-iommu: change 'depth' to int

Coverity reports an unsigned overflow when doing:

    for (; depth-- > 0; ) {

When depth = 0 inside riscv_iommu_ctx_fetch().

Building it with a recent GCC the code doesn't actually break with depth
= 0, i.e. the comparison "0-- > 0" will exit the loop instead of
proceeding,  but 'depth' will retain the overflow value afterwards.

This behavior can be compiler dependent, so change 'depth' to int to
remove this potential ambiguity.

Resolves: Coverity CID 1564783
Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104123839.533442-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d3b96a53190dc52d436c39b03fb7533fef044869
      
https://github.com/qemu/qemu/commit/d3b96a53190dc52d436c39b03fb7533fef044869
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M hw/riscv/riscv-iommu.c

  Log Message:
  -----------
  hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check

'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
'switch' right before it if 'mode' isn't 0, 8, 9 or 10.

'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.

Reported by Coverity via a "DEADCODE" ticket.

Resolves: Coverity CID 1564781
Fixes: 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104123839.533442-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b48381b1ee55053dfad6f5c10ca277bef29ee7c5
      
https://github.com/qemu/qemu/commit/b48381b1ee55053dfad6f5c10ca277bef29ee7c5
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: Set vdata.vm field for vector load/store whole register 
instructions

The vm field of the vector load/store whole register instruction's
encoding is 1.
The helper function of the vector load/store whole register instructions
may need the vdata.vm field to do some optimizations.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2f077842f2b356a086f70e54c831be53c6f0e101
      
https://github.com/qemu/qemu/commit/2f077842f2b356a086f70e54c831be53c6f0e101
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us

Because the real vl (evl) of vext_ldst_us may be different (e.g.
vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function
should be replaced by checking evl in vext_ldst_us.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 338aa15d50b37fa797677d96c091aa81a383e2a1
      
https://github.com/qemu/qemu/commit/338aa15d50b37fa797677d96c091aa81a383e2a1
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unmasked unit-stride load/store

This commit references the sve_ldN_r/sve_stN_r helper functions in ARM
target to optimize the vector unmasked unit-stride load/store
implementation with following optimizations:

* Get the page boundary
* Probing pages/resolving host memory address at the beginning if
  possible
* Provide new interface to direct access host memory
* Switch to the original slow TLB access when cross page element/violate
  page permission/violate pmp/watchpoints in page

The original element load/store interface is replaced by the new element
load/store functions with _tlb & _host postfix that means doing the
element load/store through the original softmmu flow and the direct
access host memory flow.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-4-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3333000f693e31fd9c5bf3e50f21c90b8ca1b512
      
https://github.com/qemu/qemu/commit/3333000f693e31fd9c5bf3e50f21c90b8ca1b512
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unit-stride whole register load/store

The vector unit-stride whole register load/store instructions are
similar to unmasked unit-stride load/store instructions that is suitable
to be optimized by using a direct access to host ram fast path.

Because the vector whole register load/store instructions do not need to
handle the tail agnostic, so remove the vstart early exit checking.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f00089267df8d6c9b8c8cc92aa0ba22737f6dfd2
      
https://github.com/qemu/qemu/commit/f00089267df8d6c9b8c8cc92aa0ba22737f6dfd2
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unit-stride load-only-first load instructions

The unmasked unit-stride fault-only-first load instructions are similar
to the unmasked unit-stride load/store instructions that is suitable to
be optimized by using a direct access to host ram fast path.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e32988789b63d6b09754d4812b87d5bf7ebb37b2
      
https://github.com/qemu/qemu/commit/e32988789b63d6b09754d4812b87d5bf7ebb37b2
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st 
instructions

The vector unmasked unit-stride and whole register load/store
instructions will load/store continuous memory. If the endian of both
the host and guest architecture are the same, then we can group the
element load/store to load/store more data at a time.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f8ee6f533d696b34f74cf4dcf542961776d56e4e
      
https://github.com/qemu/qemu/commit/f8ee6f533d696b34f74cf4dcf542961776d56e4e
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Inline unit-stride ld/st and corresponding functions for 
performance

In the vector unit-stride load/store helper functions. the vext_ldst_us
& vext_ldst_whole functions corresponding most of the execution time.
Inline the functions can avoid the function call overhead to improve the
helper function performance.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 13d438502b2945f52fd2aa266efb201dc776cb4b
      
https://github.com/qemu/qemu/commit/13d438502b2945f52fd2aa266efb201dc776cb4b
  Author: Quan Zhou <zhouquan@iscas.ac.cn>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: Update kvm exts to Linux v6.11

Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs.

Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-ID: 
<ada40759a79c0728652ace59579aa843cb7bf53f.1727164986.git.zhouquan@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 27652f9ca9d831c67dd447346c6ee953669255f0
      
https://github.com/qemu/qemu/commit/27652f9ca9d831c67dd447346c6ee953669255f0
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M tests/avocado/tuxrun_baselines.py
    M tests/functional/test_riscv64_tuxrun.py

  Log Message:
  -----------
  tests/functional: Convert the RV32-on-RV64 riscv test

A straggler that has been added to the Avocado framework while the
conversion to the functional framework was already in progress...
Move it over now, too!

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20241105103519.341304-1-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 32bd9e206e04111ac3bb4fabdb215060ee1076e1
      
https://github.com/qemu/qemu/commit/32bd9e206e04111ac3bb4fabdb215060ee1076e1
  Author: Dehan Meng <demeng@redhat.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M qga/commands-linux.c

  Log Message:
  -----------
  qemu-ga: Add 'Null' check and Redefine 'route'

sscanf return values are checked and add 'Null' check for
mandatory parameters. And merged redundant route and
networkroute variables.

Signed-off-by: Dehan Meng <demeng@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-ID: <20241107102155.57573-2-kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>


  Commit: ccc2dfab57bfe4fdd02288761a7e7482f352bfcc
      
https://github.com/qemu/qemu/commit/ccc2dfab57bfe4fdd02288761a7e7482f352bfcc
  Author: Dehan Meng <demeng@redhat.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M qga/commands-linux.c

  Log Message:
  -----------
  qemu-ga: Optimize var declaration and definition

Variable declarations moved to the beginning of blocks
Followed the coding style of using snake_case for variable names.
Proper initialization of param 'size_t n' to '0' for

Signed-off-by: Dehan Meng <demeng@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-ID: <20241107102155.57573-3-kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>


  Commit: 5ab1c032e6eea810142eb918c57222464482756f
      
https://github.com/qemu/qemu/commit/5ab1c032e6eea810142eb918c57222464482756f
  Author: Dehan Meng <demeng@redhat.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M qga/commands-linux.c

  Log Message:
  -----------
  qemu-ga: Avoiding freeing line prematurely

It's now only freed at the end of the function.

Signed-off-by: Dehan Meng <demeng@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-ID: <20241107102155.57573-4-kkostiuk@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>


  Commit: 0736038408308012ed34aa2135ea3b458d9cff41
      
https://github.com/qemu/qemu/commit/0736038408308012ed34aa2135ea3b458d9cff41
  Author: Stefan Berger <stefanb@linux.ibm.com>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M tests/functional/test_arm_aspeed.py

  Log Message:
  -----------
  tests: Adjust path for swtpm state to use path under /var/tmp/

To avoid AppArmor-related test failures when functional test are run from
somewhere under /mnt, adjust the path to swtpm's state to use an AppArmor-
supported path, such as /var/tmp, which is provided by the python function
tempfile.TemporaryDirectory().

An update to swtpm's AppArmor profile is also being done to support /var/tmp.

Link: 
https://lore.kernel.org/qemu-devel/CAFEAcA8A=kWLtTZ+nua-MpzqkaEjW5srOYZruZnE2tB6vmoMig@mail.gmail.com/
Link: https://github.com/stefanberger/swtpm/pull/944
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Fixes: f04cb2d00d5c ("tests/functional: Convert most Aspeed machine tests")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>


  Commit: d150b2e3e43706d23f9b65cd134702cc588dabb5
      
https://github.com/qemu/qemu/commit/d150b2e3e43706d23f9b65cd134702cc588dabb5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M hw/char/sifive_uart.c
    M hw/riscv/riscv-iommu.c
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/kvm/kvm-cpu.c
    M target/riscv/vector_helper.c
    M tests/avocado/tuxrun_baselines.py
    M tests/functional/test_riscv64_tuxrun.py

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20241107' of 
https://github.com/alistair23/qemu into staging

RISC-V PR for 9.2

* Fix broken SiFive UART on big endian hosts
* Fix IOMMU Coverity issues
* Improve the performance of vector unit-stride/whole register ld/st 
instructions
* Update kvm exts to Linux v6.11
* Convert the RV32-on-RV64 riscv test

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* tag 'pull-riscv-to-apply-20241107' of https://github.com/alistair23/qemu:
  tests/functional: Convert the RV32-on-RV64 riscv test
  target/riscv/kvm: Update kvm exts to Linux v6.11
  target/riscv: Inline unit-stride ld/st and corresponding functions for 
performance
  target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st 
instructions
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unit-stride load-only-first load instructions
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unit-stride whole register load/store
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unmasked unit-stride load/store
  target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us
  target/riscv: Set vdata.vm field for vector load/store whole register 
instructions
  hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check
  hw/riscv/riscv-iommu: change 'depth' to int
  hw/char/sifive_uart: Fix broken UART on big endian hosts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0e95022cca17e33ee435207b3e487f91e7ed24dd
      
https://github.com/qemu/qemu/commit/0e95022cca17e33ee435207b3e487f91e7ed24dd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M qga/commands-linux.c

  Log Message:
  -----------
  Merge tag 'qga-pull-2024-11-07' of https://github.com/kostyanf14/qemu into 
staging

qga-pull-2024-11-07

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# 3OMcphiCdcOpxyV1WwF5RIharrnlBzLxKxfK2Qm6O9kz+ju+3oM=
# =Vixy
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 07 Nov 2024 10:28:56 GMT
# gpg:                using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7
# gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign) 
<kkostiuk@redhat.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: C2C2 C109 EA43 C63C 1423  EB84 EF5D 5E81 61BA 84E7

* tag 'qga-pull-2024-11-07' of https://github.com/kostyanf14/qemu:
  qemu-ga: Avoiding freeing line prematurely
  qemu-ga: Optimize var declaration and definition
  qemu-ga: Add 'Null' check and Redefine 'route'

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bf674454178cae5a9c8502c6571c30227e3c100f
      
https://github.com/qemu/qemu/commit/bf674454178cae5a9c8502c6571c30227e3c100f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M tests/functional/test_arm_aspeed.py

  Log Message:
  -----------
  Merge tag 'pull-tpm-2024-11-07-1' of https://github.com/stefanberger/qemu-tpm 
into staging

Merge test 2024/11/07 v1

# -----BEGIN PGP SIGNATURE-----
#
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# G1vOhbstMXGlR94R7ratKse7zvrfRg==
# =E/yb
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 07 Nov 2024 13:01:19 GMT
# gpg:                using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211
# gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" 
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B818 B9CA DF90 89C2 D5CE  C66B 75AD 6580 2A0B 4211

* tag 'pull-tpm-2024-11-07-1' of https://github.com/stefanberger/qemu-tpm:
  tests: Adjust path for swtpm state to use path under /var/tmp/

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a1dacb66915e...bf674454178c

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