[Qemu-commits] [qemu/qemu] feef18: Merge tag 'pull-riscv-to-apply-20241107' of https:...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: feef1866d1366d651e6a3cb8c9cf1a9aabb81395
      
https://github.com/qemu/qemu/commit/feef1866d1366d651e6a3cb8c9cf1a9aabb81395
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-11-07 (Thu, 07 Nov 2024)

  Changed paths:
    M hw/char/sifive_uart.c
    M hw/riscv/riscv-iommu.c
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/kvm/kvm-cpu.c
    M target/riscv/vector_helper.c
    M tests/avocado/tuxrun_baselines.py
    M tests/functional/test_riscv64_tuxrun.py

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20241107' of 
https://github.com/alistair23/qemu into staging

RISC-V PR for 9.2

* Fix broken SiFive UART on big endian hosts
* Fix IOMMU Coverity issues
* Improve the performance of vector unit-stride/whole register ld/st 
instructions
* Update kvm exts to Linux v6.11
* Convert the RV32-on-RV64 riscv test

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* tag 'pull-riscv-to-apply-20241107' of https://github.com/alistair23/qemu:
  tests/functional: Convert the RV32-on-RV64 riscv test
  target/riscv/kvm: Update kvm exts to Linux v6.11
  target/riscv: Inline unit-stride ld/st and corresponding functions for 
performance
  target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st 
instructions
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unit-stride load-only-first load instructions
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unit-stride whole register load/store
  target/riscv: rvv: Provide a fast path using direct access to host ram for 
unmasked unit-stride load/store
  target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us
  target/riscv: Set vdata.vm field for vector load/store whole register 
instructions
  hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check
  hw/riscv/riscv-iommu: change 'depth' to int
  hw/char/sifive_uart: Fix broken UART on big endian hosts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>



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