Re: [Qemu-devel] [PATCH 2/5] softmmu templates: optionally pass CPUState to memory access functions

[Aurelien Jarno]

On Fri, Aug 24, 2012 at 05:52:29PM +0200, Andreas Färber wrote:
> Am 24.08.2012 17:35, schrieb malc:
> > On Fri, 24 Aug 2012, malc wrote:
> > 
> >> On Fri, 24 Aug 2012, Aurelien Jarno wrote:
> >>
> >>> On Sun, Mar 11, 2012 at 10:24:03PM +0000, Blue Swirl wrote:
> > 
> > [..snip..]
> > 
> >>> - On 32 bit hosts, which usually need register alignments for 64-bit
> >>>   values (at least on arm and mips), given AREG0 is a 32-bit value this
> >>             ditto ppc32, erm.. with sysv abi that is
> 
> ...which have been fixed in the v1.1 release cycle. You can take a look
> at tcg/ppc/ for how we've fixed that with alignment macros and variable.

The fix still includes one more constraint. Also the method used for PPC
doesn't apply to ARM or MIPS, as they only have 4 registers to pass
arguments, the remaining going on the stack.

> Not opposed to changing the argument order, but given that we're inches
> away from v1.2 (in Hard Freeze), it might be better to first get AREG0
> as first argument working for your favorite hosts as a bugfix and then
> do any larger optimization for v1.3.

It's what I tried to do first, but I don't think it is realistic to use
such a code for v1.2, it is complex to support all cases, and thus
likely full of bugs. Maybe we should simply disable ARM and MIPS support
for this release.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net