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[Qemu-devel] [PULL 19/43] pcie_host: expose address format
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL 19/43] pcie_host: expose address format |
Date: |
Mon, 14 Oct 2013 17:59:07 +0300 |
Callers pass in the address so it's helpful for
them to be able to decode it.
Reviewed-by: Gerd Hoffmann <address@hidden>
Tested-by: Gerd Hoffmann <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Tested-by: Igor Mammedov <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
include/hw/pci/pcie_host.h | 21 +++++++++++++++++++++
hw/pci/pcie_host.c | 21 ---------------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index bac3c67..da0f275 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -54,4 +54,25 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
hwaddr addr,
uint32_t size);
+/*
+ * PCI express ECAM (Enhanced Configuration Address Mapping) format.
+ * AKA mmcfg address
+ * bit 20 - 28: bus number
+ * bit 15 - 19: device number
+ * bit 12 - 14: function number
+ * bit 0 - 11: offset in configuration space of a given device
+ */
+#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
+#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
+#define PCIE_MMCFG_BUS_BIT 20
+#define PCIE_MMCFG_BUS_MASK 0x1ff
+#define PCIE_MMCFG_DEVFN_BIT 12
+#define PCIE_MMCFG_DEVFN_MASK 0xff
+#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
+#define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
+ PCIE_MMCFG_BUS_MASK)
+#define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
+ PCIE_MMCFG_DEVFN_MASK)
+#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
+
#endif /* PCIE_HOST_H */
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index 410ac08..c6e1b57 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -24,27 +24,6 @@
#include "hw/pci/pcie_host.h"
#include "exec/address-spaces.h"
-/*
- * PCI express mmcfig address
- * bit 20 - 28: bus number
- * bit 15 - 19: device number
- * bit 12 - 14: function number
- * bit 0 - 11: offset in configuration space of a given device
- */
-#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
-#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
-#define PCIE_MMCFG_BUS_BIT 20
-#define PCIE_MMCFG_BUS_MASK 0x1ff
-#define PCIE_MMCFG_DEVFN_BIT 12
-#define PCIE_MMCFG_DEVFN_MASK 0xff
-#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
-#define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
- PCIE_MMCFG_BUS_MASK)
-#define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
- PCIE_MMCFG_DEVFN_MASK)
-#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
-
-
/* a helper function to get a PCIDevice for a given mmconfig address */
static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
uint32_t mmcfg_addr)
--
MST
- [Qemu-devel] [PULL 10/43] hw/pcie: AER and hot-plug events must use device's interrupt, (continued)
- [Qemu-devel] [PULL 10/43] hw/pcie: AER and hot-plug events must use device's interrupt, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 09/43] hw: set interrupts using pci irq wrappers, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 11/43] hw/pci: removed irq field from PCIDevice, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 12/43] cleanup object.h: include error.h directly, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 13/43] qom: cleanup struct Error references, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 14/43] qom: add pointer to int property helpers, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 15/43] pci: fix up w64 size calculation helper, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 16/43] fw_cfg: interface to trigger callback on read, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 17/43] loader: support for unmapped ROM blobs, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 18/43] pcie_host: expose UNMAPPED macro, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 19/43] pcie_host: expose address format,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL 20/43] q35: use macro for MCFG property name, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 21/43] q35: expose mmcfg size as a property, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 23/43] acpi: add rules to compile ASL source, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 25/43] acpi: ssdt pcihp: updat generated file, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 22/43] i386: add ACPI table files from seabios, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 26/43] loader: use file path size from fw_cfg.h, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 24/43] acpi: pre-compiled ASL files, Michael S. Tsirkin, 2013/10/14
- [Qemu-devel] [PULL 27/43] i386: add bios linker/loader, Michael S. Tsirkin, 2013/10/14