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Re: [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family |
Date: |
Tue, 03 Jun 2014 11:36:45 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA
> CPUs. Since we are building common infrastructure for SPRs intialization
> to share it between 970 and POWER5+/7/..., let's add missing SPRs to
> the 970 family. Later rework of CPU class initialization will use those
> for all PowerISA CPUs.
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
> target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f7fe549..e4c9a4c 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7356,6 +7356,10 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> + spr_register(env, SPR_POWER_MMCRA, "MMCRA",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> spr_register(env, SPR_POWER_PMC1, "PMC1",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> @@ -7372,10 +7376,22 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> + spr_register(env, SPR_POWER_PMC5, "PMC5",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_POWER_PMC6, "PMC6",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> spr_register(env, SPR_POWER_SIAR, "SIAR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_SDAR, "SDAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> }
>
> static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> @@ -7388,6 +7404,10 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> spr_register(env, SPR_POWER_UPMC1, "UPMC1",
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7404,10 +7424,22 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_UPMC5, "UPMC5",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UPMC6, "UPMC6",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> spr_register(env, SPR_POWER_USIAR, "USIAR",
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_USDAR, "USDAR",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> }
>
> static void gen_spr_power5p_ear(CPUPPCState *env)
>
Similar comments on the Uxxxx SPRs as I made for patch 4. Still OK with
addressing this later.
Reviewed-by: Tom Musta <address@hidden>
- Re: [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration, (continued)
- [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family, Alexey Kardashevskiy, 2014/06/03
- Re: [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family,
Tom Musta <=
- [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR, Alexey Kardashevskiy, 2014/06/03