Re: [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs

[Tom Musta]

On 6/3/2014 9:54 PM, Alexey Kardashevskiy wrote:
> On 06/04/2014 03:58 AM, Tom Musta wrote:
>> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>>> This adds TM (Transactional Memory) SPRs.
>>>
[ ... ]

>>
>> There are user-mode impacts here as well .... although I think we are a long 
>> way off from doing anything with TM.
>>
>> The typical pattern is to default MSR enable bits to 1 ... see 
>> translate_init.c/ppc_cpu_reset:
> 
> 
> 
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -9459,19 +9459,19 @@ static void ppc_cpu_reset(CPUState *s)
>  #endif
>  #if defined(CONFIG_USER_ONLY)
>      msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
>      msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
>      msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
>      msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
>      msr |= (target_ulong)1 << MSR_PR;
> +    msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
>  #if !defined(TARGET_WORDS_BIGENDIAN)
>      msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
>  #endif
>  #endif
> 
> 
> So I'll do this and if MSR_TM is not in msr_mask (CPUs older than POWER8),
> the guest won't see it and we are fine. Correct?
> 
> 

Correct.  This is consistent with what is done with all of those other MSR bits.

> 
>>   9490  /* CPUClass::reset() */
>>   9491  static void ppc_cpu_reset(CPUState *s)
>>   9492  {
>>   9493      PowerPCCPU *cpu = POWERPC_CPU(s);
>>   9494      PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>>   9495      CPUPPCState *env = &cpu->env;
>>   9496      target_ulong msr;
>>   9497      int i;
>>   9498
>>   9499      pcc->parent_reset(s);
>>   9500
>>   9501      msr = (target_ulong)0;
>>   9502      if (0) {
>>   9503          /* XXX: find a suitable condition to enable the hypervisor 
>> mode */
>>   9504          msr |= (target_ulong)MSR_HVB;
>>   9505      }
>>   9506      msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
>>   9507      msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
>>   9508      msr |= (target_ulong)1 << MSR_EP;
>>   9509  #if defined(DO_SINGLE_STEP) && 0
>>   9510      /* Single step trace mode */
>>   9511      msr |= (target_ulong)1 << MSR_SE;
>>   9512      msr |= (target_ulong)1 << MSR_BE;
>>   9513  #endif
>>   9514  #if defined(CONFIG_USER_ONLY)
>>   9515      msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage 
>> */
>>   9516      msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
>>   9517      msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
>>   9518      msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
>>   9519      msr |= (target_ulong)1 << MSR_PR;
>>   9520  #if !defined(TARGET_WORDS_BIGENDIAN)
>>
> 
>