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Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR |
Date: |
Tue, 03 Jun 2014 12:08:17 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This makes user-privileged read/write fail if TAR facility is not enabled
> in FSCR.
>
> Since this is the very first check for enabled in FSCR facility,
> this also adds gen_fscr_facility_check() for using in spr_write_tar()/
> spr_read_tar().
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
> target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++-
> 1 file changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 6f0c36b..9b83d56 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE {
> BOOK3S_CPU_POWER8
> };
>
> +static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
> + int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_update_current_nip(opaque);
> + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> static int check_pow_970 (CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & 0x01C00000) {
> @@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void spr_read_tar(void *opaque, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_read_generic(opaque, gprn, sprn);
> +}
> +
> +static void spr_write_tar(void *opaque, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_write_generic(opaque, sprn, gprn);
> +}
> +
> static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> {
> spr_register(env, SPR_TAR, "TAR",
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_tar, &spr_write_tar,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> }
>
There are potential impacts to user mode here. If I am reading correctly, TAR
would not be accessible
in user mode.
An obvious fix would be to initialize FSCR to enable TAR access in the user
mode build targets.
- Re: [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8, (continued)
[Qemu-devel] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 24/29] KVM: target-ppc: Enable TM state migration, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64(), Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR, Alexey Kardashevskiy, 2014/06/03
- Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR,
Tom Musta <=
[Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/06/03
[Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE, Alexey Kardashevskiy, 2014/06/03