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Re: [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR
From: |
Tom Musta |
Subject: |
Re: [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR |
Date: |
Tue, 03 Jun 2014 11:59:03 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined in
> PowerISA 2.05.
>
> Signed-off-by: Alexey Kardashevskiy <address@hidden>
> ---
> Changes:
> v4:
> * disabled reading it from user space
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 97f01ca..8f43b37 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_BOOKE_GIVOR8 (0x1BB)
> #define SPR_BOOKE_GIVOR13 (0x1BC)
> #define SPR_BOOKE_GIVOR14 (0x1BD)
> +#define SPR_TIR (0x1BE)
> #define SPR_BOOKE_SPEFSCR (0x200)
> #define SPR_Exxx_BBEAR (0x201)
> #define SPR_Exxx_BBTAR (0x202)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 17163e7..c41d289 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7509,6 +7509,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_pir,
> 0x00000000);
> +
> + spr_register(env, SPR_TIR, "TIR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> }
>
> static void gen_spr_book3s_purr(CPUPPCState *env)
>
It looks like TIR gets added to both P7 and P8. Intentional? (TIR was added
in ISA 2.07 ... not sure if it existed in P7 implementations or not).
- [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8, (continued)
- [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR, Alexey Kardashevskiy, 2014/06/03
- Re: [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR,
Tom Musta <=
- [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs, Alexey Kardashevskiy, 2014/06/03
- [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8, Alexey Kardashevskiy, 2014/06/03