[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to a separate func |
Date: |
Tue, 10 Jun 2014 01:04:22 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
cpu-exec.c | 5 ++---
target-arm/cpu.h | 16 ++++++++++++++++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 38e5f02..a579ffc 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -478,7 +478,7 @@ int cpu_exec(CPUArchState *env)
}
#elif defined(TARGET_ARM)
if (interrupt_request & CPU_INTERRUPT_FIQ
- && !(env->daif & PSTATE_F)) {
+ && arm_excp_unmasked(cpu, EXCP_FIQ)) {
cpu->exception_index = EXCP_FIQ;
cc->do_interrupt(cpu);
next_tb = 0;
@@ -493,8 +493,7 @@ int cpu_exec(CPUArchState *env)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && ((IS_M(env) && env->regs[15] < 0xfffffff0)
- || !(env->daif & PSTATE_I))) {
+ && arm_excp_unmasked(cpu, EXCP_IRQ)) {
cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index de00e01..2f262a5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1126,6 +1126,22 @@ bool write_cpustate_to_list(ARMCPU *cpu);
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
+{
+ CPUARMState *env = cs->env_ptr;
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ return !(env->daif & PSTATE_F);
+ case EXCP_IRQ:
+ return ((IS_M(env) && env->regs[15] < 0xfffffff0)
+ || !(env->daif & PSTATE_I));
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
static inline CPUARMState *cpu_init(const char *cpu_model)
{
ARMCPU *cpu = cpu_arm_init(cpu_model);
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v2 06/17] target-arm: Add FAR_EL2 and 3, (continued)
- [Qemu-devel] [PATCH v2 07/17] target-arm: Add HCR_EL2, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 08/17] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 09/17] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to a separate func,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v2 11/17] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 12/17] target-arm: A64: Correct updates to FAR and ESR on exceptions, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 13/17] target-arm: Use uint16_t in syndrome generators with 16bit imms, Edgar E. Iglesias, 2014/06/09