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[Qemu-devel] [PATCH v2 12/17] target-arm: A64: Correct updates to FAR an
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v2 12/17] target-arm: A64: Correct updates to FAR and ESR on exceptions |
Date: |
Tue, 10 Jun 2014 01:04:24 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Not all exception types update both FAR and ESR.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper-a64.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 7d94a74..c91005f 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -466,18 +466,16 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->exception.syndrome);
}
- env->cp15.esr_el[new_el] = env->exception.syndrome;
- env->cp15.far_el[new_el] = env->exception.vaddress;
-
switch (cs->exception_index) {
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
+ env->cp15.far_el[new_el] = env->exception.vaddress;
qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
env->cp15.far_el[new_el]);
- break;
case EXCP_BKPT:
case EXCP_UDEF:
case EXCP_SWI:
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
break;
case EXCP_IRQ:
addr += 0x80;
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v2 07/17] target-arm: Add HCR_EL2, (continued)
- [Qemu-devel] [PATCH v2 08/17] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 09/17] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 11/17] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 12/17] target-arm: A64: Correct updates to FAR and ESR on exceptions,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v2 13/17] target-arm: Use uint16_t in syndrome generators with 16bit imms, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 15/17] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/06/09
- [Qemu-devel] [PATCH v2 16/17] target-arm: Add IRQ and FIQ routing to EL2 and 3, Edgar E. Iglesias, 2014/06/09