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[Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R13 & R14 |
Date: |
Wed, 11 Jun 2014 01:54:45 +0200 |
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 060664f..903aa01 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -153,8 +153,8 @@ typedef struct CPUARMState {
/* Banked registers. */
uint64_t banked_spsr[8];
- uint32_t banked_r13[6];
- uint32_t banked_r14[6];
+ uint32_t banked_r13[8];
+ uint32_t banked_r14[8];
/* These hold r8-r12. */
uint32_t usr_regs[5];
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 3bcc7cc..5ed495e 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -234,8 +234,8 @@ const VMStateDescription vmstate_arm_cpu = {
},
VMSTATE_UINT32(env.spsr, ARMCPU),
VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
- VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
- VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
+ VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
+ VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v3 02/32] target-arm: move Aarch32 SCR into security reglist, (continued)
- [Qemu-devel] [PATCH v3 07/32] target-arm: add non-secure Translation Block flag, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 05/32] target-arm: reject switching to monitor mode, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 15/32] target-arm: add NSACR register, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 08/32] target-arm: A32: Emulate the SMC instruction, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R13 & R14,
Fabian Aggeler <=
- [Qemu-devel] [PATCH v3 14/32] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 06/32] target-arm: make arm_current_pl() return PL3, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 09/32] target-arm: extend Aarch32 async excp masking, Fabian Aggeler, 2014/06/10