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[Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support |
Date: |
Wed, 11 Jun 2014 01:54:59 +0200 |
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 15 +++++++++------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c76a31c..221b847 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -212,6 +212,7 @@ typedef struct CPUARMState {
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
uint64_t vbar_el[4]; /* vector base address register */
+ uint64_t mvbar; /* (monitor) vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4bf203e..f9b2374 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2286,6 +2286,9 @@ static const ARMCPRegInfo security_cp_reginfo[] = {
.access = PL3_RW | PL1_R, .resetvalue = 0,
.writefn = nsacr_write, .readfn = nsacr_read,
.fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) },
+ { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
+ .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
REGINFO_SENTINEL
};
@@ -3837,16 +3840,16 @@ void arm_cpu_do_interrupt(CPUState *cs)
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
- /* High vectors. */
- if (env->cp15.c1_sys & SCTLR_V) {
- /* when enabled, base address cannot be remapped. */
+
+ if (new_mode == ARM_CPU_MODE_MON) {
+ addr += env->cp15.mvbar;
+ } else if (env->cp15.c1_sys & SCTLR_V) {
+ /* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000;
} else {
/* ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
- * This register is only followed in non-monitor mode, and has a secure
- * and un-secure copy. Since the cpu is always in a un-secure operation
- * and is never in monitor mode this feature is always active.
+ * This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
*/
addr += env->cp15.vbar_el[1];
--
1.8.3.2
- [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function, (continued)
Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function, Edgar E. Iglesias, 2014/06/17
[Qemu-devel] [PATCH v3 10/32] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support,
Fabian Aggeler <=
[Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 19/32] target-arm: insert Aarch32 cpregs twice into hashtable, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 20/32] target-arm: arrayfying fieldoffset for banking, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 21/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 22/32] target-arm: make CSSELR banked, Fabian Aggeler, 2014/06/10