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Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() functi
From: |
Sergey Fedorov |
Subject: |
Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function |
Date: |
Wed, 11 Jun 2014 16:17:37 +0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 11.06.2014 03:54, Fabian Aggeler wrote:
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions/EL3.
> arm_is_secure_below_el3() returns true if CPU is in secure state
> below EL3.
>
> Signed-off-by: Sergey Fedorov <address@hidden>
> Signed-off-by: Fabian Aggeler <address@hidden>
> ---
> target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 903aa01..cb0da6b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -710,6 +710,44 @@ static inline int arm_feature(CPUARMState *env, int
> feature)
> return (env->features & (1ULL << feature)) != 0;
> }
>
> +
> +/* Return true if exception level below EL3 is in secure state */
> +static inline bool arm_is_secure_below_el3(CPUARMState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + if (arm_feature(env, ARM_FEATURE_EL3)) {
> + return !(env->cp15.scr_el3 & SCR_NS);
> + } else if (arm_feature(env, ARM_FEATURE_EL2)) {
> + return false;
> + } else {
> + /* IMPDEF: QEMU defaults to non-secure */
> + return false;
> + }
> +#else
> + return false;
> +#endif
> +}
> +
> +/* Return true if the processor is in secure state */
> +static inline bool arm_is_secure(CPUARMState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + if (arm_feature(env, ARM_FEATURE_EL3)) {
> + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) {
> + /* CPU currently in Aarch64 state and EL3 */
> + return true;
> + } else if (!env->aarch64 &&
> + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
> + /* CPU currently in Aarch32 state and monitor mode */
> + return true;
> + }
Hi Fabian,
Why don't use arm_current_pl() from patch 6 to determine EL here?
Best regards,
Sergey
> + }
> + return arm_is_secure_below_el3(env);
> +#else
> + return false;
> +#endif
> +}
> +
> /* Return true if the specified exception level is running in AArch64 state.
> */
> static inline bool arm_el_is_aa64(CPUARMState *env, int el)
> {
- [Qemu-devel] [PATCH v3 14/32] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, (continued)
- [Qemu-devel] [PATCH v3 14/32] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 06/32] target-arm: make arm_current_pl() return PL3, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 09/32] target-arm: extend Aarch32 async excp masking, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 12/32] target-arm: use dedicated target_el function, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 11/32] target-arm: add async excp target_el&mode function, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function, Fabian Aggeler, 2014/06/10
- Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function,
Sergey Fedorov <=
Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function, Edgar E. Iglesias, 2014/06/17
[Qemu-devel] [PATCH v3 10/32] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers, Fabian Aggeler, 2014/06/10