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[Qemu-devel] [PATCH v3 04/25] tcg-ppc64: Relax register restrictions in
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 04/25] tcg-ppc64: Relax register restrictions in tcg_out_mem_long |
Date: |
Fri, 20 Jun 2014 07:13:20 -0700 |
In order to be able to use tcg_out_ld/st sensibly with scratch
registers, assert only when we'd incorrectly clobber a scratch.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 951a392..dbe9c5c 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -714,10 +714,9 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
TCGReg base, tcg_target_long offset)
{
tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
+ bool is_store = false;
TCGReg rs = TCG_REG_R2;
- assert(rt != TCG_REG_R2 && base != TCG_REG_R2);
-
switch (opi) {
case LD: case LWA:
align = 3;
@@ -725,19 +724,22 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
default:
if (rt != TCG_REG_R0) {
rs = rt;
+ break;
}
break;
case STD:
align = 3;
- break;
+ /* FALLTHRU */
case STB: case STH: case STW:
+ is_store = true;
break;
}
/* For unaligned, or very large offsets, use the indexed form. */
if (offset & align || offset != (int32_t)offset) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, orig);
- tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
+ tcg_debug_assert(rs != base && (!is_store || rs != rt));
+ tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
+ tcg_out32(s, opx | TAB(rt, base, rs));
return;
}
--
1.9.3
- [Qemu-devel] [PATCH v3 00/25] Merge ppc32/ppc64 tcg backends, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 01/25] tcg-ppc: Use uintptr_t in ppc_tb_set_jmp_target, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 02/25] tcg-ppc64: Avoid some hard-codings of TCG_TYPE_I64, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 03/25] tcg-ppc64: Move functions around, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 04/25] tcg-ppc64: Relax register restrictions in tcg_out_mem_long,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 05/25] tcg-ppc64: Use tcg_out_{ld, st, cmp} internally, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 06/25] tcg-ppc64: Make TCG_AREG0 and TCG_REG_CALL_STACK enum constants, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 07/25] tcg-ppc64: Move call macros out of tcg-target.h, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 08/25] tcg-ppc64: Fix TCG_TARGET_CALL_STACK_OFFSET, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 09/25] tcg-ppc64: Better parameterize the stack frame, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 10/25] tcg-ppc64: Use the correct test in tcg_out_call, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 11/25] tcg-ppc64: Support the ppc64 elfv2 ABI, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 12/25] tcg-ppc64: Adjust tcg_out_call for ELFv2, Richard Henderson, 2014/06/20
- [Qemu-devel] [PATCH v3 13/25] tcg-ppc64: Merge 32-bit ABIs into the prologue / frame code, Richard Henderson, 2014/06/20