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[Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R
From: |
greg . bellows |
Subject: |
[Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14 |
Date: |
Mon, 30 Jun 2014 18:09:03 -0500 |
From: Fabian Aggeler <address@hidden>
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5accbde..ffc51f2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -153,8 +153,8 @@ typedef struct CPUARMState {
/* Banked registers. */
uint64_t banked_spsr[8];
- uint32_t banked_r13[6];
- uint32_t banked_r14[6];
+ uint32_t banked_r13[8];
+ uint32_t banked_r14[8];
/* These hold r8-r12. */
uint32_t usr_regs[5];
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 3bcc7cc..5ed495e 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -234,8 +234,8 @@ const VMStateDescription vmstate_arm_cpu = {
},
VMSTATE_UINT32(env.spsr, ARMCPU),
VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
- VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
- VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
+ VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
+ VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
--
1.8.3.2
- [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14,
greg . bellows <=
- [Qemu-devel] [PATCH v4 05/33] target-arm: reject switching to monitor mode, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 07/33] target-arm: add non-secure Translation Block flag, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 08/33] target-arm: A32: Emulate the SMC instruction, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode, greg . bellows, 2014/06/30