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[Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs wi
From: |
greg . bellows |
Subject: |
[Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions |
Date: |
Mon, 30 Jun 2014 18:09:01 -0500 |
From: Fabian Aggeler <address@hidden>
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d77be99..46ee1fe 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -551,6 +551,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
cpu->mvfr0 = 0x11111111;
@@ -637,6 +638,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
cpu->mvfr0 = 0x11110222;
@@ -703,6 +705,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
@@ -769,6 +772,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
--
1.8.3.2
- [Qemu-devel] [PATCH v4 00/33] target-arm: add Security Extensions for CPUs, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 05/33] target-arm: reject switching to monitor mode, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions,
greg . bellows <=
- [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 07/33] target-arm: add non-secure Translation Block flag, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 08/33] target-arm: A32: Emulate the SMC instruction, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 14/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register, greg . bellows, 2014/06/30