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[Qemu-devel] [PATCH 04/13] target-s390x: change CHRL and CGHRL format to
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 04/13] target-s390x: change CHRL and CGHRL format to RIL-b |
Date: |
Mon, 1 Jun 2015 23:24:48 +0200 |
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.
Cc: Alexander Graf <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-s390x/insn-data.def | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index f83445a..7649098 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -159,8 +159,8 @@
C(0xe55c, CHSI, SIL, GIE, m1_32s, i2, 0, 0, 0, cmps64)
C(0xe558, CGHSI, SIL, GIE, m1_64, i2, 0, 0, 0, cmps64)
/* COMPARE HALFWORD RELATIVE LONG */
- C(0xc605, CHRL, RIL_a, GIE, r1_o, mri2_32s, 0, 0, 0, cmps32)
- C(0xc604, CGHRL, RIL_a, GIE, r1_o, mri2_64, 0, 0, 0, cmps64)
+ C(0xc605, CHRL, RIL_b, GIE, r1_o, mri2_32s, 0, 0, 0, cmps32)
+ C(0xc604, CGHRL, RIL_b, GIE, r1_o, mri2_64, 0, 0, 0, cmps64)
/* COMPARE LOGICAL */
C(0x1500, CLR, RR_a, Z, r1, r2, 0, 0, 0, cmpu32)
--
2.1.4
- Re: [Qemu-devel] [PATCH 02/13] target-s390x: fix CLGIT instruction, (continued)
- [Qemu-devel] [PATCH 05/13] target-s390x: move STORE CLOCK FAST to the correct facility, Aurelien Jarno, 2015/06/01
- [Qemu-devel] [PATCH 04/13] target-s390x: change CHRL and CGHRL format to RIL-b,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 08/13] target-s390x: implement TRANSLATE AND TEST instruction, Aurelien Jarno, 2015/06/01
- [Qemu-devel] [PATCH 01/13] target-s390x: fix exception for invalid operation code, Aurelien Jarno, 2015/06/01
- [Qemu-devel] [PATCH 07/13] target-s390x: implement LOAD FP INTEGER instructions, Aurelien Jarno, 2015/06/01
- [Qemu-devel] [PATCH 11/13] target-s390x: implement miscellaneous-instruction-extensions facility, Aurelien Jarno, 2015/06/01