Re: [Qemu-devel] [PATCH RESEND v1 5/8] target-microblaze: Convert pvr-full to a CPU property

[Alistair Francis]

On Fri, Jun 5, 2015 at 10:44 AM, Edgar E. Iglesias
<address@hidden> wrote:
> On Thu, Jun 04, 2015 at 11:23:57AM +1000, Alistair Francis wrote:
>> Originally the pvr-full PVR bits were manually set for each machine. This
>> is a hassle and difficult to read, instead set them based on the CPU
>> properties.
>>
>> Signed-off-by: Alistair Francis <address@hidden>
>> ---
>>  target-microblaze/cpu-qom.h |    1 +
>>  target-microblaze/cpu.c     |    7 ++++---
>>  target-microblaze/helper.c  |    4 ++--
>>  3 files changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
>> index b6c6374..799f5b8 100644
>> --- a/target-microblaze/cpu-qom.h
>> +++ b/target-microblaze/cpu-qom.h
>> @@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
>>          bool dcache_writeback;
>>          bool endi;
>>          bool version_mask;
>> +        bool pvr_full;
>>      } cfg;
>>
>>      CPUMBState env;
>> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
>> index 849c737..329d4d5 100644
>> --- a/target-microblaze/cpu.c
>> +++ b/target-microblaze/cpu.c
>> @@ -91,8 +91,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
>> **errp)
>>
>>      qemu_init_vcpu(cs);
>>
>> -    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
>> -                       | PVR0_USE_BARREL_MASK \
>> +    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
>>                         | PVR0_USE_DIV_MASK \
>>                         | PVR0_USE_HW_MUL_MASK \
>>                         | PVR0_USE_EXC_MASK \
>> @@ -116,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error 
>> **errp)
>>                          (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) |
>>                          (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) |
>>                          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
>> -                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0);
>> +                        (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0) |
>> +                        (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0);
>>
>>      env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
>>                          (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>> @@ -178,6 +178,7 @@ static Property mb_properties[] = {
>>                       false),
>>      DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false),
>>      DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, 
>> false),
>> +    DEFINE_PROP_BOOL("pvr-full", MicroBlazeCPU, cfg.pvr_full, true),
>
> This is another one with wierdo dts mapping.
>
> You can look our tree hw/microblaze/microblaze_generic_fdt.c to figure it out.

Thanks Edgar

Alistair

>
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>
>> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
>> index b310c2b..55b92e2 100644
>> --- a/target-microblaze/helper.c
>> +++ b/target-microblaze/helper.c
>> @@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, 
>> int rw,
>>      mmu_available = 0;
>>      if (cpu->cfg.usemmu) {
>>          mmu_available = 1;
>> -        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
>> -            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
>> +        if (cpu->cfg.pvr_full &&
>> +            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
>>              mmu_available = 0;
>>          }
>>      }
>> --
>> 1.7.1
>>
>