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[Qemu-devel] [PULL 18/30] target-arm: implement SCTLR.EE
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/30] target-arm: implement SCTLR.EE |
Date: |
Fri, 4 Mar 2016 11:41:41 +0000 |
From: Peter Crosthwaite <address@hidden>
Implement SCTLR.EE bit which controls data endianess for exceptions
and page table translations. SCTLR.EE is mirrored to the CPSR.E bit
on exception entry.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0a0e85d..eaded41 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6241,6 +6241,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
env->condexec_bits = 0;
/* Switch to the new mode, and to the correct instruction set. */
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
+ /* Set new mode endianness */
+ env->uncached_cpsr &= ~CPSR_E;
+ if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
+ env->uncached_cpsr |= ~CPSR_E;
+ }
env->daif |= mask;
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
* and we should just guard the thumb mode on V4 */
@@ -6527,6 +6532,12 @@ static inline bool
regime_translation_disabled(CPUARMState *env,
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}
+static inline bool regime_translation_big_endian(CPUARMState *env,
+ ARMMMUIdx mmu_idx)
+{
+ return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
+}
+
/* Return the TCR controlling this translation regime */
static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
@@ -6849,7 +6860,11 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
if (fi->s1ptw) {
return 0;
}
- return address_space_ldl(as, addr, attrs, NULL);
+ if (regime_translation_big_endian(env, mmu_idx)) {
+ return address_space_ldl_be(as, addr, attrs, NULL);
+ } else {
+ return address_space_ldl_le(as, addr, attrs, NULL);
+ }
}
static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
@@ -6867,7 +6882,11 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
if (fi->s1ptw) {
return 0;
}
- return address_space_ldq(as, addr, attrs, NULL);
+ if (regime_translation_big_endian(env, mmu_idx)) {
+ return address_space_ldq_be(as, addr, attrs, NULL);
+ } else {
+ return address_space_ldq_le(as, addr, attrs, NULL);
+ }
}
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
--
1.9.1
- [Qemu-devel] [PULL 07/30] hw/arm/virt: Load bios image to MemoryRegion, not physaddr, (continued)
- [Qemu-devel] [PULL 07/30] hw/arm/virt: Load bios image to MemoryRegion, not physaddr, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 14/30] target-arm: cpu: Move cpu_is_big_endian to header, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 22/30] target-arm: introduce tbflag for endianness, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 06/30] loader: Add load_image_mr() to load ROM image to a MemoryRegion, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 19/30] target-arm: pass DisasContext to gen_aa32_ld*/st*, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 08/30] hw/arm/virt: Make first flash device Secure-only if booting secure, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 15/30] arm: cpu: handle BE32 user-mode as BE, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 17/30] linux-user: arm: handle CPSR.E correctly in strex emulation, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 28/30] arm: boot: Support big-endian elfs, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 05/30] hw/arm/virt: Provide a secure-only RAM if booting in Secure mode, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 18/30] target-arm: implement SCTLR.EE,
Peter Maydell <=
- [Qemu-devel] [PULL 23/30] target-arm: implement setend, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 26/30] loader: load_elf(): Add doc comment, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 09/30] hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is provided, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 11/30] linux-user: arm: fix coding style for some linux-user signal functions, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 13/30] target-arm: implement SCTLR.B, drop bswap_code, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 21/30] target-arm: a64: Add endianness support, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 25/30] loader: add API to load elf header, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 24/30] target-arm: implement BE32 mode in system emulation, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 30/30] target-arm: Only trap SRS from S-EL1 if specified mode is MON, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 29/30] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR, Peter Maydell, 2016/03/04