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[Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent P
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container |
Date: |
Tue, 15 Mar 2016 09:59:26 +0000 |
Implement generic MIPS Coherent Processing System (CPS) which in this
commit just creates VPs, but it will serve as a container also for
other components like Global Configuration Registers and Cluster Power
Controller.
Signed-off-by: Leon Alrae <address@hidden>
---
default-configs/mips-softmmu-common.mak | 1 +
hw/mips/Makefile.objs | 1 +
hw/mips/cps.c | 108 ++++++++++++++++++++++++++++++++
include/hw/mips/cps.h | 40 ++++++++++++
4 files changed, 150 insertions(+)
create mode 100644 hw/mips/cps.c
create mode 100644 include/hw/mips/cps.h
diff --git a/default-configs/mips-softmmu-common.mak
b/default-configs/mips-softmmu-common.mak
index 37009a3..18e4beb 100644
--- a/default-configs/mips-softmmu-common.mak
+++ b/default-configs/mips-softmmu-common.mak
@@ -30,3 +30,4 @@ CONFIG_I8259=y
CONFIG_MC146818RTC=y
CONFIG_ISA_TESTDEV=y
CONFIG_EMPTY_SLOT=y
+CONFIG_MIPS_CPS=y
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 9633f3a..9352a1c 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -3,3 +3,4 @@ obj-y += addr.o cputimer.o mips_int.o
obj-$(CONFIG_JAZZ) += mips_jazz.o
obj-$(CONFIG_FULONG) += mips_fulong2e.o
obj-y += gt64xxx_pci.o
+obj-$(CONFIG_MIPS_CPS) += cps.o
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
new file mode 100644
index 0000000..782aa2b
--- /dev/null
+++ b/hw/mips/cps.c
@@ -0,0 +1,108 @@
+/*
+ * Coherent Processing System emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/mips/cps.h"
+#include "hw/mips/mips.h"
+#include "hw/mips/cpudevs.h"
+
+qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
+{
+ MIPSCPU *cpu = MIPS_CPU(first_cpu);
+ CPUMIPSState *env = &cpu->env;
+
+ assert(pin_number < s->num_irq);
+
+ /* TODO: return GIC pins once implemented */
+ return env->irq[pin_number];
+}
+
+static void mips_cps_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ MIPSCPSState *s = MIPS_CPS(obj);
+
+ /* Cover entire address space as there do not seem to be any
+ * constraints for the base address of CPC and GIC. */
+ memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
+ sysbus_init_mmio(sbd, &s->container);
+}
+
+static void main_cpu_reset(void *opaque)
+{
+ MIPSCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(cs);
+
+ /* All VPs are halted on reset. Leave powering up to CPC. */
+ cs->halted = 1;
+}
+
+static void mips_cps_realize(DeviceState *dev, Error **errp)
+{
+ MIPSCPSState *s = MIPS_CPS(dev);
+ CPUMIPSState *env;
+ MIPSCPU *cpu;
+ int i;
+
+ for (i = 0; i < s->num_vp; i++) {
+ cpu = cpu_mips_init(s->cpu_model);
+ if (cpu == NULL) {
+ error_setg(errp, "%s: CPU initialization failed\n", __func__);
+ return;
+ }
+ env = &cpu->env;
+
+ /* Init internal devices */
+ cpu_mips_irq_init_cpu(env);
+ cpu_mips_clock_init(env);
+ qemu_register_reset(main_cpu_reset, cpu);
+ }
+}
+
+static Property mips_cps_properties[] = {
+ DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
+ DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 8),
+ DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void mips_cps_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = mips_cps_realize;
+ dc->props = mips_cps_properties;
+}
+
+static const TypeInfo mips_cps_info = {
+ .name = TYPE_MIPS_CPS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MIPSCPSState),
+ .instance_init = mips_cps_init,
+ .class_init = mips_cps_class_init,
+};
+
+static void mips_cps_register_types(void)
+{
+ type_register_static(&mips_cps_info);
+}
+
+type_init(mips_cps_register_types)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
new file mode 100644
index 0000000..fb3528a
--- /dev/null
+++ b/include/hw/mips/cps.h
@@ -0,0 +1,40 @@
+/*
+ * Coherent Processing System emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_CPS_H
+#define MIPS_CPS_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_MIPS_CPS "mips-cps"
+#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
+
+typedef struct MIPSCPSState {
+ SysBusDevice parent_obj;
+
+ uint32_t num_vp;
+ uint32_t num_irq;
+ char *cpu_model;
+
+ MemoryRegion container;
+} MIPSCPSState;
+
+qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
+
+#endif
--
2.1.0
- [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container,
Leon Alrae <=
- [Qemu-devel] [PATCH v2 02/11] target-mips: add CMGCRBase register, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 03/11] hw/mips: add initial Global Config Register support, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 05/11] hw/mips: add initial Cluster Power Controller support, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 06/11] hw/mips/cps: create CPC block inside CPS, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 07/11] hw/mips_malta: remove CPUMIPSState from the write_bootloader(), Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 08/11] hw/mips_malta: remove redundant irq and clock init, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 10/11] hw/mips_malta: add CPS to Malta board, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 09/11] hw/mips_malta: move CPU creation to a separate function, Leon Alrae, 2016/03/15
- [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU, Leon Alrae, 2016/03/15