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Re: [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 reg
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs |
Date: |
Wed, 16 Mar 2016 12:15:33 +1100 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Mon, Mar 14, 2016 at 05:56:40PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <address@hidden>
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
And this looks like a fix for 2.6 to me.
> ---
> target-ppc/cpu.h | 3 +++
> target-ppc/translate_init.c | 12 ++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 9e1ef10b7dc6..9ed406cf111b 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1359,7 +1359,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
> ifetch)
> #define SPR_SRR1 (0x01B)
> #define SPR_CFAR (0x01C)
> #define SPR_AMR (0x01D)
> +#define SPR_ACOP (0x01F)
> #define SPR_BOOKE_PID (0x030)
> +#define SPR_BOOKS_PID (0x030)
> #define SPR_BOOKE_DECAR (0x036)
> #define SPR_BOOKE_CSRR0 (0x03A)
> #define SPR_BOOKE_CSRR1 (0x03B)
> @@ -1713,6 +1715,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
> ifetch)
> #define SPR_POWER_SPMC1 (0x37C)
> #define SPR_POWER_SPMC2 (0x37D)
> #define SPR_POWER_MMCRS (0x37E)
> +#define SPR_WORT (0x37F)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f88bdf7b3cd1..22afeef2731a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8175,6 +8175,18 @@ static void gen_spr_power8_book4(CPUPPCState *env)
> &spr_read_generic, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0);
> + spr_register_kvm(env, SPR_ACOP, "ACOP",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_ACOP, 0);
> + spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PID, 0);
> + spr_register_kvm(env, SPR_WORT, "WORT",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_WORT, 0);
> #endif
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB, (continued)
- [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs, Cédric Le Goater, 2016/03/14
- [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register, Cédric Le Goater, 2016/03/14
- [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8, Cédric Le Goater, 2016/03/14
- [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode, Cédric Le Goater, 2016/03/14
- [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR, Cédric Le Goater, 2016/03/14