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[Qemu-devel] [PATCH v2 6/8] target-mips: check CP0 enabled for CACHE ins
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v2 6/8] target-mips: check CP0 enabled for CACHE instruction also in R6 |
Date: |
Fri, 25 Mar 2016 13:49:35 +0000 |
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
/* Treat as NOP. */
break;
case R6_OPC_CACHE:
+ check_cp0_enabled(ctx);
/* Treat as NOP. */
break;
case R6_OPC_SC:
--
2.7.4
- [Qemu-devel] [PATCH v2 0/8] mips: implement Inter-Thread Communication Unit, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 2/8] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 4/8] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 5/8] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 3/8] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 1/8] hw/mips: implement ITC Configuration Tags and Storage Cells, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 6/8] target-mips: check CP0 enabled for CACHE instruction also in R6,
Leon Alrae <=
- [Qemu-devel] [PATCH v2 8/8] hw/mips/cps: enable ITU for multithreading processors, Leon Alrae, 2016/03/25
- [Qemu-devel] [PATCH v2 7/8] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/03/25