[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 00/21] target-mips queue for 2.6
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 00/21] target-mips queue for 2.6 |
Date: |
Tue, 29 Mar 2016 10:56:44 +0100 |
Hi,
Here's MIPS pull request which adds initial implementation of MIPS Coherent
Processing System including Cluster Power Controller and Global Config
Registers allowing the guest to control the start of other Virtual
Processors after reset. Also, this pullreq adds Inter-Thread Communication
Unit and MAAR.
Thanks,
Leon
Cc: Peter Maydell <address@hidden>
Cc: Aurelien Jarno <address@hidden>
The following changes since commit b68a80139e37e806f004237e55311ebc42151434:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160324' into
staging (2016-03-24 16:24:02 +0000)
are available in the git repository at:
git://github.com/lalrae/qemu.git tags/mips-20160329
for you to fetch changes up to e9f517b73dab520de05b871359d2beedf8b04e53:
target-mips: add MAAR, MAARI register (2016-03-28 19:27:09 +0100)
----------------------------------------------------------------
MIPS patches 2016-03-29
Changes:
* add initial MIPS CPS support
* implement ITU block
* implement MAAR
----------------------------------------------------------------
Leon Alrae (17):
hw/mips: implement generic MIPS Coherent Processing System container
hw/mips/cps: create GCR block inside CPS
hw/mips: add initial Cluster Power Controller support
hw/mips/cps: create CPC block inside CPS
hw/mips_malta: remove CPUMIPSState from the write_bootloader()
hw/mips_malta: remove redundant irq and clock init
hw/mips_malta: move CPU creation to a separate function
hw/mips_malta: add CPS to Malta board
target-mips: enable CM GCR in MIPS64R6-generic CPU
hw/mips: implement ITC Configuration Tags and Storage Cells
hw/mips: implement ITC Storage - Control View
hw/mips: implement ITC Storage - Empty/Full Sync and Try Views
hw/mips: implement ITC Storage - P/V Sync and Try Views
hw/mips: implement ITC Storage - Bypass View
target-mips: check CP0 enabled for CACHE instruction also in R6
target-mips: make ITC Configuration Tags accessible to the CPU
hw/mips/cps: enable ITU for multithreading processors
Yongbok Kim (4):
target-mips: add CMGCRBase register
hw/mips: add initial Global Config Register support
target-mips: use CP0_CHECK for gen_m{f|t}hc0
target-mips: add MAAR, MAARI register
default-configs/mips-softmmu-common.mak | 2 +
hw/mips/Makefile.objs | 1 +
hw/mips/cps.c | 179 +++++++++++
hw/mips/mips_malta.c | 118 ++++---
hw/misc/Makefile.objs | 3 +
hw/misc/mips_cmgcr.c | 159 ++++++++++
hw/misc/mips_cpc.c | 176 +++++++++++
hw/misc/mips_itu.c | 525 ++++++++++++++++++++++++++++++++
include/hw/mips/cps.h | 46 +++
include/hw/misc/mips_cmgcr.h | 59 ++++
include/hw/misc/mips_cpc.h | 47 +++
include/hw/misc/mips_itu.h | 72 +++++
target-mips/cpu.h | 16 +-
target-mips/helper.h | 9 +
target-mips/machine.c | 6 +-
target-mips/op_helper.c | 85 +++++-
target-mips/translate.c | 189 +++++++++---
target-mips/translate_init.c | 6 +-
18 files changed, 1619 insertions(+), 79 deletions(-)
create mode 100644 hw/mips/cps.c
create mode 100644 hw/misc/mips_cmgcr.c
create mode 100644 hw/misc/mips_cpc.c
create mode 100644 hw/misc/mips_itu.c
create mode 100644 include/hw/mips/cps.h
create mode 100644 include/hw/misc/mips_cmgcr.h
create mode 100644 include/hw/misc/mips_cpc.h
create mode 100644 include/hw/misc/mips_itu.h
- [Qemu-devel] [PULL 00/21] target-mips queue for 2.6,
Leon Alrae <=
- [Qemu-devel] [PULL 06/21] hw/mips/cps: create CPC block inside CPS, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 15/21] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 19/21] hw/mips/cps: enable ITU for multithreading processors, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader(), Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 13/21] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 04/21] hw/mips/cps: create GCR block inside CPS, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock init, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 09/21] hw/mips_malta: move CPU creation to a separate function, Leon Alrae, 2016/03/29