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[Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock init |
Date: |
Tue, 29 Mar 2016 10:56:52 +0100 |
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.
These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/mips/mips_malta.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index cbfdb78..b70948d 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1133,10 +1133,6 @@ void mips_malta_init(MachineState *machine)
/* Board ID = 0x420 (Malta Board with CoreLV) */
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
- /* Init internal devices */
- cpu_mips_irq_init_cpu(env);
- cpu_mips_clock_init(env);
-
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
--
2.1.0
- [Qemu-devel] [PULL 00/21] target-mips queue for 2.6, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 06/21] hw/mips/cps: create CPC block inside CPS, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 15/21] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 19/21] hw/mips/cps: enable ITU for multithreading processors, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader(), Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 13/21] hw/mips: implement ITC Storage - Control View, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 04/21] hw/mips/cps: create GCR block inside CPS, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock init,
Leon Alrae <=
- [Qemu-devel] [PULL 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 09/21] hw/mips_malta: move CPU creation to a separate function, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 01/21] hw/mips: implement generic MIPS Coherent Processing System container, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 10/21] hw/mips_malta: add CPS to Malta board, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 03/21] hw/mips: add initial Global Config Register support, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 05/21] hw/mips: add initial Cluster Power Controller support, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 16/21] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/03/29