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[Qemu-devel] [PULL 14/21] hw/mips: implement ITC Storage - Empty/Full Sy
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views |
Date: |
Tue, 29 Mar 2016 10:56:58 +0100 |
Empty/Full Synchronized and Try views can be used to access FIFO cells.
Store to the FIFO cell pushes the value into the queue, load pops the oldest
element from the queue. Cell's Full and Empty bits are automatically updated
to reflect new state of the cell.
Empty/Full Synchronized View causes the issuing thread to block when FIFO is
empty while thread is performing a read, or FIFO is full while thread is
performing a write.
Empty/Full Try View never blocks the thread. If cell is full then write is
ignored, if cell is empty then load returns 0.
Trap bit (i.e. Gating Storage exceptions) not implemented.
Store Conditional support for E/F Try View (i.e. indicate failure if FIFO
is full) not implemented.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/misc/mips_itu.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 742656d..ae59ae4 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -159,6 +159,26 @@ static inline ITCStorageCell *get_cell(MIPSITUState *s,
return &s->cell[cell_idx];
}
+static void wake_blocked_threads(ITCStorageCell *c)
+{
+ CPUState *cs;
+ CPU_FOREACH(cs) {
+ if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
+ cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
+ }
+ }
+ c->blocked_threads = 0;
+}
+
+static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
+{
+ c->blocked_threads |= 1ULL << current_cpu->cpu_index;
+ cpu_restore_state(current_cpu, current_cpu->mem_io_pc);
+ current_cpu->halted = 1;
+ current_cpu->exception_index = EXCP_HLT;
+ cpu_loop_exit(current_cpu);
+}
+
/* ITC Control View */
static inline uint64_t view_control_read(ITCStorageCell *c)
@@ -182,6 +202,87 @@ static inline void view_control_write(ITCStorageCell *c,
uint64_t val)
}
}
+/* ITC Empty/Full View */
+
+static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
+{
+ uint64_t ret = 0;
+
+ if (!c->tag.FIFO) {
+ return 0;
+ }
+
+ c->tag.F = 0;
+
+ if (blocking && c->tag.E) {
+ block_thread_and_exit(c);
+ }
+
+ if (c->blocked_threads) {
+ wake_blocked_threads(c);
+ }
+
+ if (c->tag.FIFOPtr > 0) {
+ ret = c->data[c->fifo_out];
+ c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
+ c->tag.FIFOPtr--;
+ }
+
+ if (c->tag.FIFOPtr == 0) {
+ c->tag.E = 1;
+ }
+
+ return ret;
+}
+
+static uint64_t view_ef_sync_read(ITCStorageCell *c)
+{
+ return view_ef_common_read(c, true);
+}
+
+static uint64_t view_ef_try_read(ITCStorageCell *c)
+{
+ return view_ef_common_read(c, false);
+}
+
+static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
+ bool blocking)
+{
+ if (!c->tag.FIFO) {
+ return;
+ }
+
+ c->tag.E = 0;
+
+ if (blocking && c->tag.F) {
+ block_thread_and_exit(c);
+ }
+
+ if (c->blocked_threads) {
+ wake_blocked_threads(c);
+ }
+
+ if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
+ int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
+ c->data[idx] = val;
+ c->tag.FIFOPtr++;
+ }
+
+ if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
+ c->tag.F = 1;
+ }
+}
+
+static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
+{
+ view_ef_common_write(c, val, true);
+}
+
+static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
+{
+ view_ef_common_write(c, val, false);
+}
+
static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
{
MIPSITUState *s = (MIPSITUState *)opaque;
@@ -193,6 +294,12 @@ static uint64_t itc_storage_read(void *opaque, hwaddr
addr, unsigned size)
case ITCVIEW_CONTROL:
ret = view_control_read(cell);
break;
+ case ITCVIEW_EF_SYNC:
+ ret = view_ef_sync_read(cell);
+ break;
+ case ITCVIEW_EF_TRY:
+ ret = view_ef_try_read(cell);
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_read: Bad ITC View %d\n", (int)view);
@@ -213,6 +320,12 @@ static void itc_storage_write(void *opaque, hwaddr addr,
uint64_t data,
case ITCVIEW_CONTROL:
view_control_write(cell, data);
break;
+ case ITCVIEW_EF_SYNC:
+ view_ef_sync_write(cell, data);
+ break;
+ case ITCVIEW_EF_TRY:
+ view_ef_try_write(cell, data);
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_write: Bad ITC View %d\n", (int)view);
--
2.1.0
- [Qemu-devel] [PULL 04/21] hw/mips/cps: create GCR block inside CPS, (continued)
- [Qemu-devel] [PULL 04/21] hw/mips/cps: create GCR block inside CPS, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 08/21] hw/mips_malta: remove redundant irq and clock init, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 09/21] hw/mips_malta: move CPU creation to a separate function, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 01/21] hw/mips: implement generic MIPS Coherent Processing System container, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 10/21] hw/mips_malta: add CPS to Malta board, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 03/21] hw/mips: add initial Global Config Register support, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 05/21] hw/mips: add initial Cluster Power Controller support, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views,
Leon Alrae <=
- [Qemu-devel] [PULL 16/21] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 18/21] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 02/21] target-mips: add CMGCRBase register, Leon Alrae, 2016/03/29
- [Qemu-devel] [PULL 21/21] target-mips: add MAAR, MAARI register, Leon Alrae, 2016/03/29
- Re: [Qemu-devel] [PULL 00/21] target-mips queue for 2.6, Peter Maydell, 2016/03/29