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[Qemu-devel] [PATCH v18 13/29] hw/registerfields.h: Add 8bit and 16bit r
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v18 13/29] hw/registerfields.h: Add 8bit and 16bit register macros |
Date: |
Fri, 7 Jun 2019 17:37:09 +0200 |
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..a0bb0654d6 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 4 };
+#define REG8(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 2 };
+
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -34,6 +42,12 @@
MAKE_64BIT_MASK(shift, length)};
/* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field) \
+ extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field) \
+ extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
#define FIELD_EX32(storage, reg, field) \
extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +63,22 @@
* Assigning values larger then the target field will result in
* compilation warnings.
*/
+#define FIELD_DP8(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint8_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+#define FIELD_DP16(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint16_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
#define FIELD_DP32(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
@@ -57,7 +87,7 @@
d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH, v.v); \
d; })
-#define FIELD_DP64(storage, reg, field, val) ({ \
+#define FIELD_DP64(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
} v = { .v = val }; \
--
2.20.1
- Re: [Qemu-devel] [PATCH v18 04/29] !fixup target/rx: CPU definition, (continued)
[Qemu-devel] [PATCH v18 15/29] target/rx: Add RX to SysEmuTarget, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 19/29] MAINTAINERS: Add RX, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 17/29] hw/rx: Honor -accel qtest, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 16/29] tests: Add rx to machine-none-test.c, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 14/29] target/rx: Convert to CPUClass::tlb_fill, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 12/29] qemu/bitops.h: Add extract8 and extract16, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 13/29] hw/registerfields.h: Add 8bit and 16bit register macros,
Philippe Mathieu-Daudé <=
[Qemu-devel] [PATCH v18 05/29] !fixup target/rx: CPU definition, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 09/29] hw/char: RX62N serial communication interface (SCI), Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 07/29] hw/intc: RX62N interrupt controller (ICUa), Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 02/29] target/rx: TCG helper, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 03/29] target/rx: CPU definition, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 08/29] hw/timer: RX62N internal timer modules, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 06/29] target/rx: RX disassembler, Philippe Mathieu-Daudé, 2019/06/07
[Qemu-devel] [PATCH v18 10/29] hw/rx: RX Target hardware definition, Philippe Mathieu-Daudé, 2019/06/07