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Re: [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition
From: |
Igor Mammedov |
Subject: |
Re: [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition |
Date: |
Sun, 16 Jun 2019 20:13:55 +0200 |
On Sun, 16 Jun 2019 23:28:15 +0900
Yoshinori Sato <address@hidden> wrote:
> Signed-off-by: Yoshinori Sato <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
> Message-Id: <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to
> extable array, use rx_cpu_tlb_fill() extracted from patch of
> Yoshinori Sato 'Convert to CPUClass::tlb_fill']
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
>
> Signed-off-by: Yoshinori Sato <address@hidden>
> ---
[...]
> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
> new file mode 100644
> index 0000000000..4147c5c939
> --- /dev/null
> +++ b/target/rx/cpu.c
[...]
> +static void rx_cpu_list_entry(gpointer data, gpointer user_data)
> +{
> + const char *typename = object_class_get_name(OBJECT_CLASS(data));
> + int len = strlen(typename) - strlen(RX_CPU_TYPE_SUFFIX);
> +
> + qemu_printf("%.*s\n", len, typename);
> +}
> +
> +void rx_cpu_list(void)
> +{
> + GSList *list;
> + list = object_class_get_list_sorted(TYPE_RX_CPU, false);
> + g_slist_foreach(list, rx_cpu_list_entry, NULL);
> + g_slist_free(list);
> +}
> +
> +static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
> +{
> + ObjectClass *oc;
> + char *typename;
> +
> + oc = object_class_by_name(cpu_model);
> + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
> + !object_class_is_abstract(oc)) {
> + return oc;
> + }
> +
> + typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
> + oc = object_class_by_name(typename);
> + if (oc != NULL && object_class_is_abstract(oc)) {
> + oc = NULL;
> + }
> + g_free(typename);
> +
> + if (!oc) {
> + /* default to rx62n */
> + oc = object_class_by_name(TYPE_RX62N_CPU);
> + }
please address comments made on v19 version of the patch
and reply with fixed v21 here (assuming it doesn't break follow up patches)
> + return oc;
> +}
> +
[...]
- [Qemu-devel] [PATCH v20 05/24] target/rx: simplify rx_cpu_class_by_name, (continued)
- [Qemu-devel] [PATCH v20 05/24] target/rx: simplify rx_cpu_class_by_name, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 17/24] target/rx: Move rx_load_image to rx-virt., Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 18/24] hw/rx: Honor -accel qtest, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 24/24] BootLinuxConsoleTest: Test the RX-Virt machine, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 01/24] target/rx: TCG translation, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 20/24] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 16/24] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition, Yoshinori Sato, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition,
Igor Mammedov <=
- [Qemu-devel] [PATCH v20 19/24] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 22/24] Add rx-softmmu, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 13/24] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 23/24] MAINTAINERS: Add RX, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16bit register macros, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 02/24] target/rx: TCG helper, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 11/24] target/rx: Collect all bytes during disassembly, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 06/24] target/rx: RX disassembler, Yoshinori Sato, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16