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Re: [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16b
From: |
Igor Mammedov |
Subject: |
Re: [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16bit register macros |
Date: |
Sun, 16 Jun 2019 21:06:41 +0200 |
On Sun, 16 Jun 2019 23:28:33 +0900
Yoshinori Sato <address@hidden> wrote:
> From: Philippe Mathieu-Daudé <address@hidden>
>
> Some RX peripheral using 8bit and 16bit registers.
> Added 8bit and 16bit APIs.
probably should go before 13/24 (i.e. before actual users start using it)
this patch causes checkpatch errors but it uses macro magic style
common to registerfields.h.
we probably don't wish to fix existing code style at the moment.
> Signed-off-by: Yoshinori Sato <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> Message-Id: <address@hidden>
> Tested-by: Philippe Mathieu-Daudé <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> index 2659a58737..a0bb0654d6 100644
> --- a/include/hw/registerfields.h
> +++ b/include/hw/registerfields.h
> @@ -22,6 +22,14 @@
> enum { A_ ## reg = (addr) }; \
> enum { R_ ## reg = (addr) / 4 };
>
> +#define REG8(reg, addr) \
> + enum { A_ ## reg = (addr) }; \
> + enum { R_ ## reg = (addr) };
> +
> +#define REG16(reg, addr) \
> + enum { A_ ## reg = (addr) }; \
> + enum { R_ ## reg = (addr) / 2 };
> +
> /* Define SHIFT, LENGTH and MASK constants for a field within a register */
>
> /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and
> R_FOO_BAR_LENGTH
> @@ -34,6 +42,12 @@
> MAKE_64BIT_MASK(shift, length)};
>
> /* Extract a field from a register */
> +#define FIELD_EX8(storage, reg, field) \
> + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH)
> +#define FIELD_EX16(storage, reg, field) \
> + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH)
> #define FIELD_EX32(storage, reg, field) \
> extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> R_ ## reg ## _ ## field ## _LENGTH)
> @@ -49,6 +63,22 @@
> * Assigning values larger then the target field will result in
> * compilation warnings.
> */
> +#define FIELD_DP8(storage, reg, field, val) ({ \
> + struct { \
> + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> + } v = { .v = val }; \
> + uint8_t d; \
> + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH, v.v); \
> + d; })
> +#define FIELD_DP16(storage, reg, field, val) ({ \
> + struct { \
> + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> + } v = { .v = val }; \
> + uint16_t d; \
> + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH, v.v); \
> + d; })
> #define FIELD_DP32(storage, reg, field, val) ({ \
> struct { \
> unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> @@ -57,7 +87,7 @@
> d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> R_ ## reg ## _ ## field ## _LENGTH, v.v); \
> d; })
> -#define FIELD_DP64(storage, reg, field, val) ({ \
> +#define FIELD_DP64(storage, reg, field, val) ({ \
> struct { \
> unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> } v = { .v = val }; \
- [Qemu-devel] [PATCH v20 01/24] target/rx: TCG translation, (continued)
- [Qemu-devel] [PATCH v20 01/24] target/rx: TCG translation, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 20/24] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 16/24] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 19/24] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 22/24] Add rx-softmmu, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 13/24] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 23/24] MAINTAINERS: Add RX, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16bit register macros, Yoshinori Sato, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16bit register macros,
Igor Mammedov <=
- [Qemu-devel] [PATCH v20 02/24] target/rx: TCG helper, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 11/24] target/rx: Collect all bytes during disassembly, Yoshinori Sato, 2019/06/16
- [Qemu-devel] [PATCH v20 06/24] target/rx: RX disassembler, Yoshinori Sato, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16
- Re: [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support, no-reply, 2019/06/16