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[Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions
|
From: |
Jan Bobek |
|
Subject: |
[Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions |
|
Date: |
Mon, 1 Jul 2019 00:35:30 -0400 |
Add SSE2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek <address@hidden>
---
x86.risu | 153 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/x86.risu b/x86.risu
index c29b210..9b63d6b 100644
--- a/x86.risu
+++ b/x86.risu
@@ -15,179 +15,332 @@
# Data Transfer Instructions
MOVD MMX 00001111 011 d 1110 !emit { modrm(mod => MOD_DIRECT,
rm => ~REG_ESP); }
MOVD_mem MMX 00001111 011 d 1110 !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 4); }
+MOVD SSE2 00001111 011 d 1110 !emit { data16(); modrm(mod =>
MOD_DIRECT, rm => ~REG_ESP); }
+MOVD_mem SSE2 00001111 011 d 1110 !emit { data16(); modrm(mod =>
~MOD_DIRECT); mem(size => 4); }
MOVQ MMX 00001111 011 d 1110 !emit { rex(w => 1); modrm(mod =>
MOD_DIRECT, rm => ~REG_ESP); }
MOVQ_mem MMX 00001111 011 d 1110 !emit { rex(w => 1); modrm(mod =>
~MOD_DIRECT); mem(size => 8); }
+MOVQ SSE2 00001111 011 d 1110 !emit { data16(); rex(w => 1);
modrm(mod => MOD_DIRECT, rm => ~REG_ESP); }
+MOVQ_mem SSE2 00001111 011 d 1110 !emit { data16(); rex(w => 1);
modrm(mod => ~MOD_DIRECT); mem(size => 8); }
MOVQ_mm MMX 00001111 011 d 1111 !emit { modrm(); mem(size => 8); }
+MOVQ_xmm1 SSE2 00001111 01111110 !emit { rep(); modrm(); mem(size =>
8); }
+MOVQ_xmm2 SSE2 00001111 11010110 !emit { data16(); modrm(); mem(size
=> 8); }
MOVAPS SSE 00001111 0010100 d !emit { modrm(); mem(size => 16,
align => 16); }
+MOVAPD SSE2 00001111 0010100 d !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+MOVDQA SSE2 00001111 011 d 1111 !emit { data16(); modrm();
mem(size => 16, align => 16); }
MOVUPS SSE 00001111 0001000 d !emit { modrm(); mem(size => 16); }
+MOVUPD SSE2 00001111 0001000 d !emit { data16(); modrm(); mem(size
=> 16); }
+MOVDQU SSE2 00001111 011 d 1111 !emit { rep(); modrm(); mem(size
=> 16); }
MOVSS SSE 00001111 0001000 d !emit { rep(); modrm(); mem(size =>
4); }
+MOVSD SSE2 00001111 0001000 d !emit { repne(); modrm(); mem(size
=> 8); }
+
+MOVQ2DQ SSE2 00001111 11010110 !emit { rep(); modrm(mod =>
MOD_DIRECT); }
+MOVDQ2Q SSE2 00001111 11010110 !emit { repne(); modrm(mod =>
MOD_DIRECT); }
MOVLPS SSE 00001111 0001001 d !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 8); }
+MOVLPD SSE2 00001111 0001001 d !emit { data16(); modrm(mod =>
~MOD_DIRECT); mem(size => 8); }
MOVHPS SSE 00001111 0001011 d !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 8); }
+MOVHPD SSE2 00001111 0001011 d !emit { data16(); modrm(mod =>
~MOD_DIRECT); mem(size => 8); }
MOVLHPS SSE 00001111 00010110 !emit { modrm(mod => MOD_DIRECT); }
MOVHLPS SSE 00001111 00010010 !emit { modrm(mod => MOD_DIRECT); }
PMOVMSKB SSE 00001111 11010111 !emit { modrm(mod => MOD_DIRECT, reg
=> ~REG_ESP); }
+PMOVMSKB SSE2 00001111 11010111 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => ~REG_ESP); }
MOVMSKPS SSE 00001111 01010000 !emit { modrm(mod => MOD_DIRECT, reg
=> ~REG_ESP); }
+MOVMKSPD SSE2 00001111 01010000 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => ~REG_ESP); }
# Arithmetic Instructions
PADDB MMX 00001111 11111100 !emit { modrm(); mem(size => 8); }
+PADDB SSE2 00001111 11111100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDW MMX 00001111 11111101 !emit { modrm(); mem(size => 8); }
+PADDW SSE2 00001111 11111101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDD MMX 00001111 11111110 !emit { modrm(); mem(size => 8); }
+PADDD SSE2 00001111 11111110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDQ MMX 00001111 11010100 !emit { modrm(); mem(size => 8); }
+PADDQ SSE2 00001111 11010100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDSB MMX 00001111 11101100 !emit { modrm(); mem(size => 8); }
+PADDSB SSE2 00001111 11101100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDSW MMX 00001111 11101101 !emit { modrm(); mem(size => 8); }
+PADDSW SSE2 00001111 11101101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDUSB MMX 00001111 11011100 !emit { modrm(); mem(size => 8); }
+PADDUSB SSE2 00001111 11011100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PADDUSW MMX 00001111 11011101 !emit { modrm(); mem(size => 8); }
+PADDUSW SSE2 00001111 11011101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
ADDPS SSE 00001111 01011000 !emit { modrm(); mem(size => 16,
align => 16); }
+ADDPD SSE2 00001111 01011000 !emit { data16(); modrm(); mem(size
=> 16, align => 16) }
ADDSS SSE 00001111 01011000 !emit { rep(); modrm(); mem(size =>
4); }
+ADDSD SSE2 00001111 01011000 !emit { repne(); modrm(); mem(size
=> 8); }
PSUBB MMX 00001111 11111000 !emit { modrm(); mem(size => 8); }
+PSUBB SSE2 00001111 11111000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSUBW MMX 00001111 11111001 !emit { modrm(); mem(size => 8); }
+PSUBW SSE2 00001111 11111001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSUBD MMX 00001111 11111010 !emit { modrm(); mem(size => 8); }
+PSUBD SSE2 00001111 11111010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PSUBQ_64 SSE2 00001111 11111011 !emit { modrm(); mem(size => 8); }
+PSUBQ SSE2 00001111 11111011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSUBSB MMX 00001111 11101000 !emit { modrm(); mem(size => 8); }
+PSUBSB SSE2 00001111 11101000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSUBSW MMX 00001111 11101001 !emit { modrm(); mem(size => 8); }
+PSUBSW SSE2 00001111 11101001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSUBUSB MMX 00001111 11011000 !emit { modrm(); mem(size => 8); }
+PSUBUSB SSE2 00001111 11011000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSUBUSW MMX 00001111 11011001 !emit { modrm(); mem(size => 8); }
+PSUBUSW SSE2 00001111 11011001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
SUBPS SSE 00001111 01011100 !emit { modrm(); mem(size => 16,
align => 16); }
+SUBPD SSE2 00001111 01011100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
SUBSS SSE 00001111 01011100 !emit { rep(); modrm(); mem(size =>
4); }
+SUBSD SSE2 00001111 01011100 !emit { repne(); modrm(); mem(size
=> 8); }
PMULLW MMX 00001111 11010101 !emit { modrm(); mem(size => 8); }
+PMULLW SSE2 00001111 11010101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PMULHW MMX 00001111 11100101 !emit { modrm(); mem(size => 8); }
+PMULHW SSE2 00001111 11100101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PMULHUW SSE 00001111 11100100 !emit { modrm(); mem(size => 8); }
+PMULHUW SSE2 00001111 11100100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMULUDQ_64 SSE2 00001111 11110100 !emit { modrm(); mem(size => 8); }
+PMULUDQ SSE2 00001111 11110100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MULPS SSE 00001111 01011001 !emit { modrm(); mem(size => 16,
align => 16); }
+MULPD SSE2 00001111 01011001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MULSS SSE 00001111 01011001 !emit { rep(); modrm(); mem(size =>
4); }
+MULSD SSE2 00001111 01011001 !emit { repne(); modrm(); mem(size
=> 8); }
PMADDWD MMX 00001111 11110101 !emit { modrm(); mem(size => 8); }
+PMADDWD SSE2 00001111 11110101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
DIVPS SSE 00001111 01011110 !emit { modrm(); mem(size => 16,
align => 16); }
+DIVPD SSE2 00001111 01011110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
DIVSS SSE 00001111 01011110 !emit { rep(); modrm(); mem(size =>
4); }
+DIVSD SSE2 00001111 01011110 !emit { repne(); modrm(); mem(size
=> 8); }
RCPPS SSE 00001111 01010011 !emit { modrm(); mem(size => 16,
align => 16); }
RCPSS SSE 00001111 01010011 !emit { rep(); modrm(); mem(size =>
4); }
SQRTPS SSE 00001111 01010001 !emit { modrm(); mem(size => 16,
align => 16); }
+SQRTPD SSE2 00001111 01010001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
SQRTSS SSE 00001111 01010001 !emit { rep(); modrm(); mem(size =>
4); }
+SQRTSD SSE2 00001111 01010001 !emit { repne(); modrm(); mem(size
=> 8); }
RSQRTPS SSE 00001111 01010010 !emit { modrm(); mem(size => 16,
align => 16); }
RSQRTSS SSE 00001111 01010010 !emit { rep(); modrm(); mem(size =>
4); }
PMINUB SSE 00001111 11011010 !emit { modrm(); mem(size => 8); }
+PMINUB SSE2 00001111 11011010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PMINSW SSE 00001111 11101010 !emit { modrm(); mem(size => 8); }
+PMINSW SSE2 00001111 11101010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MINPS SSE 00001111 01011101 !emit { modrm(); mem(size => 16,
align => 16); }
+MINPD SSE2 00001111 01011101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size =>
4); }
+MINSD SSE2 00001111 01011101 !emit { repne(); modrm(); mem(size
=> 8); }
PMAXUB SSE 00001111 11011110 !emit { modrm(); mem(size => 8); }
+PMAXUB SSE2 00001111 11011110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PMAXSW SSE 00001111 11101110 !emit { modrm(); mem(size => 8); }
+PMAXSW SSE2 00001111 11101110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size => 16,
align => 16); }
+MAXPD SSE2 00001111 01011111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MAXSS SSE 00001111 01011111 !emit { rep(); modrm(); mem(size =>
4); }
+MAXSD SSE2 00001111 01011111 !emit { repne(); modrm(); mem(size
=> 8); }
PAVGB SSE 00001111 11100000 !emit { modrm(); mem(size => 8); }
+PAVGB SSE2 00001111 11100000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PAVGW SSE 00001111 11100011 !emit { modrm(); mem(size => 8); }
+PAVGW SSE2 00001111 11100011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size => 8); }
+PSADBW SSE2 00001111 11110110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
# Comparison Instructions
PCMPEQB MMX 00001111 01110100 !emit { modrm(); mem(size => 8); }
+PCMPEQB SSE2 00001111 01110100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPEQW MMX 00001111 01110101 !emit { modrm(); mem(size => 8); }
+PCMPEQW SSE2 00001111 01110101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPEQD MMX 00001111 01110110 !emit { modrm(); mem(size => 8); }
+PCMPEQD SSE2 00001111 01110110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPGTB MMX 00001111 01100100 !emit { modrm(); mem(size => 8); }
+PCMPGTB SSE2 00001111 01100100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPGTW MMX 00001111 01100101 !emit { modrm(); mem(size => 8); }
+PCMPGTW SSE2 00001111 01100101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPGTD MMX 00001111 01100110 !emit { modrm(); mem(size => 8); }
+PCMPGTD SSE2 00001111 01100110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size => 16,
align => 16); imm(size => 1); }
+CMPPD SSE2 00001111 11000010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); imm(size => 1); }
CMPSS SSE 00001111 11000010 !emit { rep(); modrm(); mem(size =>
4); imm(size => 1); }
+CMPSD SSE2 00001111 11000010 !emit { repne(); modrm(); mem(size
=> 8); imm(size => 1); }
UCOMISS SSE 00001111 00101110 !emit { modrm(); mem(size => 4); }
+UCOMISD SSE2 00001111 00101110 !emit { data16(); modrm(); mem(size
=> 8); }
+
COMISS SSE 00001111 00101111 !emit { modrm(); mem(size => 4); }
+COMISD SSE2 00001111 00101111 !emit { data16(); modrm(); mem(size
=> 8); }
# Logical Instructions
PAND MMX 00001111 11011011 !emit { modrm(); mem(size => 8); }
+PAND SSE2 00001111 11011011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
ANDPS SSE 00001111 01010100 !emit { modrm(); mem(size => 16,
align => 16); }
+ANDPD SSE2 00001111 01010100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PANDN MMX 00001111 11011111 !emit { modrm(); mem(size => 8); }
+PANDN SSE2 00001111 11011111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
ANDNPS SSE 00001111 01010101 !emit { modrm(); mem(size => 16,
align => 16); }
+ANDNPD SSE2 00001111 01010101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
POR MMX 00001111 11101011 !emit { modrm(); mem(size => 8); }
+POR SSE2 00001111 11101011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
ORPS SSE 00001111 01010110 !emit { modrm(); mem(size => 16,
align => 16); }
+ORPD SSE2 00001111 01010110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PXOR MMX 00001111 11101111 !emit { modrm(); mem(size => 8); }
+PXOR SSE2 00001111 11101111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
XORPS SSE 00001111 01010111 !emit { modrm(); mem(size => 16,
align => 16); }
+XORPD SSE2 00001111 01010111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
# Shift and Rotate Instructions
PSLLW MMX 00001111 11110001 !emit { modrm(); mem(size => 8); }
+PSLLW SSE2 00001111 11110001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSLLD MMX 00001111 11110010 !emit { modrm(); mem(size => 8); }
+PSLLD SSE2 00001111 11110010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSLLQ MMX 00001111 11110011 !emit { modrm(); mem(size => 8); }
+PSLLQ SSE2 00001111 11110011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PSLLDQ SSE2 00001111 01110011 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 7); imm(size => 1); }
PSLLW_imm MMX 00001111 01110001 !emit { modrm(mod => MOD_DIRECT, reg
=> 6); imm(size => 1); }
+PSLLW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 6); imm(size => 1); }
PSLLD_imm MMX 00001111 01110010 !emit { modrm(mod => MOD_DIRECT, reg
=> 6); imm(size => 1); }
+PSLLD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 6); imm(size => 1); }
PSLLQ_imm MMX 00001111 01110011 !emit { modrm(mod => MOD_DIRECT, reg
=> 6); imm(size => 1); }
+PSLLQ_imm SSE2 00001111 01110011 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 6); imm(size => 1); }
PSRLW MMX 00001111 11010001 !emit { modrm(); mem(size => 8); }
+PSRLW SSE2 00001111 11010001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSRLD MMX 00001111 11010010 !emit { modrm(); mem(size => 8); }
+PSRLD SSE2 00001111 11010010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSRLQ MMX 00001111 11010011 !emit { modrm(); mem(size => 8); }
+PSRLQ SSE2 00001111 11010011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PSRLDQ SSE2 00001111 01110011 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 3); imm(size => 1); }
PSRLW_imm MMX 00001111 01110001 !emit { modrm(mod => MOD_DIRECT, reg
=> 2); imm(size => 1); }
+PSRLW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 2); imm(size => 1); }
PSRLD_imm MMX 00001111 01110010 !emit { modrm(mod => MOD_DIRECT, reg
=> 2); imm(size => 1); }
+PSRLD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 2); imm(size => 1); }
PSRLQ_imm MMX 00001111 01110011 !emit { modrm(mod => MOD_DIRECT, reg
=> 2); imm(size => 1); }
+PSRLQ_imm SSE2 00001111 01110011 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 2); imm(size => 1); }
PSRAW MMX 00001111 11100001 !emit { modrm(); mem(size => 8); }
+PSRAW SSE2 00001111 11100001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSRAD MMX 00001111 11100010 !emit { modrm(); mem(size => 8); }
+PSRAD SSE2 00001111 11100010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSRAW_imm MMX 00001111 01110001 !emit { modrm(mod => MOD_DIRECT, reg
=> 4); imm(size => 1); }
+PSRAW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 4); imm(size => 1); }
PSRAD_imm MMX 00001111 01110010 !emit { modrm(mod => MOD_DIRECT, reg
=> 4); imm(size => 1); }
+PSRAD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => 4); imm(size => 1); }
# Shuffle, Unpack, Blend, Insert, Extract, Broadcast, Permute, Scatter
Instructions
PACKSSWB MMX 00001111 01100011 !emit { modrm(); mem(size => 8); }
+PACKSSWB SSE2 00001111 01100011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PACKSSDW MMX 00001111 01101011 !emit { modrm(); mem(size => 8); }
+PACKSSDW SSE2 00001111 01101011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PACKUSWB MMX 00001111 01100111 !emit { modrm(); mem(size => 8); }
+PACKUSWB SSE2 00001111 01100111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PUNPCKHBW MMX 00001111 01101000 !emit { modrm(); mem(size => 8); }
+PUNPCKHBW SSE2 00001111 01101000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PUNPCKHWD MMX 00001111 01101001 !emit { modrm(); mem(size => 8); }
+PUNPCKHWD SSE2 00001111 01101001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PUNPCKHDQ MMX 00001111 01101010 !emit { modrm(); mem(size => 8); }
+PUNPCKHDQ SSE2 00001111 01101010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PUNPCKHQDQ SSE2 00001111 01101101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PUNPCKLBW MMX 00001111 01100000 !emit { modrm(); mem(size => 4); }
+PUNPCKLBW SSE2 00001111 01100000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PUNPCKLWD MMX 00001111 01100001 !emit { modrm(); mem(size => 4); }
+PUNPCKLWD SSE2 00001111 01100001 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PUNPCKLDQ MMX 00001111 01100010 !emit { modrm(); mem(size => 4); }
+PUNPCKLDQ SSE2 00001111 01100010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PUNPCKLQDQ SSE2 00001111 01101100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
UNPCKLPS SSE 00001111 00010100 !emit { modrm(); mem(size => 16,
align => 16); }
+UNPCKLPD SSE2 00001111 00010100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
UNPCKHPS SSE 00001111 00010101 !emit { modrm(); mem(size => 16,
align => 16); }
+UNPCKHPD SSE2 00001111 00010101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PSHUFW SSE 00001111 01110000 !emit { modrm(); mem(size => 8);
imm(size => 1); }
+PSHUFLW SSE2 00001111 01110000 !emit { repne(); modrm(); mem(size
=> 16, align => 16); imm(size => 1); }
+PSHUFHW SSE2 00001111 01110000 !emit { rep(); modrm(); mem(size =>
16, align => 16); imm(size => 1); }
+PSHUFD SSE2 00001111 01110000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); imm(size => 1); }
+
SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size => 16,
align => 16); imm(size => 1); }
+SHUFPD SSE2 00001111 11000110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); imm(size => 1); }
PINSRW SSE 00001111 11000100 !emit { modrm(); mem(size => 2);
imm(size => 1); }
+PINSRW SSE2 00001111 11000100 !emit { data16(); modrm(); mem(size
=> 2); imm(size => 1); }
+
PEXTRW_reg SSE 00001111 11000101 !emit { modrm(mod => MOD_DIRECT, reg
=> ~REG_ESP); imm(size => 1); }
+PEXTRW_reg SSE2 00001111 11000101 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => ~REG_ESP); imm(size => 1); }
# Conversion Instructions
CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size => 8); }
CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size =>
4); }
CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w => 1); modrm();
mem(size => 8); }
+CVTPI2PD SSE2 00001111 00101010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+CVTSI2SD SSE2 00001111 00101010 !emit { repne(); modrm(); mem(size
=> 4); }
+CVTSI2SD_64 SSE2 00001111 00101010 !emit { repne(); rex(w => 1);
modrm(); mem(size => 8); }
CVTPS2PI SSE 00001111 00101101 !emit { modrm(); mem(size => 8); }
CVTSS2SI SSE 00001111 00101101 !emit { rep(); modrm(reg =>
~REG_ESP); mem(size => 4); }
CVTSS2SI_64 SSE 00001111 00101101 !emit { rep(); rex(w => 1);
modrm(reg => ~REG_ESP); mem(size => 4); }
+CVTPD2PI SSE2 00001111 00101101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+CVTSD2SI SSE2 00001111 00101101 !emit { repne(); modrm(reg =>
~REG_ESP); mem(size => 8); }
+CVTSD2SI_64 SSE2 00001111 00101101 !emit { repne(); rex(w => 1);
modrm(reg => ~REG_ESP); mem(size => 8); }
CVTTPS2PI SSE 00001111 00101100 !emit { modrm(); mem(size => 8); }
CVTTSS2SI SSE 00001111 00101100 !emit { rep(); modrm(reg =>
~REG_ESP); mem(size => 4); }
CVTTSS2SI_64 SSE 00001111 00101100 !emit { rep(); rex(w => 1);
modrm(reg => ~REG_ESP); mem(size => 4); }
+CVTTPD2PI SSE2 00001111 00101100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+CVTTSD2SI SSE2 00001111 00101100 !emit { repne(); modrm(reg =>
~REG_ESP); mem(size => 8); }
+CVTTSD2SI_64 SSE2 00001111 00101100 !emit { repne(); rex(w => 1);
modrm(reg => ~REG_ESP); mem(size => 8); }
+
+CVTPD2DQ SSE2 00001111 11100110 !emit { repne(); modrm(); mem(size
=> 16, align => 16); }
+CVTTPD2DQ SSE2 00001111 11100110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+CVTDQ2PD SSE2 00001111 11100110 !emit { rep(); modrm(); mem(size =>
8); }
+
+CVTPS2PD SSE2 00001111 01011010 !emit { modrm(); mem(size => 8); }
+CVTPD2PS SSE2 00001111 01011010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+CVTSS2SD SSE2 00001111 01011010 !emit { rep(); modrm(); mem(size =>
4); }
+CVTSD2SS SSE2 00001111 01011010 !emit { repne(); modrm(); mem(size
=> 8); }
+
+CVTDQ2PS SSE2 00001111 01011011 !emit { modrm(); mem(size => 16,
align => 16); }
+CVTPS2DQ SSE2 00001111 01011011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+CVTTPS2DQ SSE2 00001111 01011011 !emit { rep(); modrm(); mem(size =>
16, align => 16); }
# Cacheability Control, Prefetch, and Instruction Ordering Instructions
MASKMOVQ SSE 00001111 11110111 !emit { modrm(mod => MOD_DIRECT);
mem(size => 8, base => REG_EDI); }
+MASKMOVDQU SSE2 00001111 11110111 !emit { data16(); modrm(mod =>
MOD_DIRECT); mem(size => 16, base => REG_EDI); }
+
MOVNTPS SSE 00001111 00101011 !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 16, align => 16); }
+MOVNTPD SSE2 00001111 00101011 !emit { data16(); modrm(mod =>
~MOD_DIRECT); mem(size => 16, align => 16); }
+
+MOVNTI SSE2 00001111 11000011 !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 4); }
+MOVNTI_64 SSE2 00001111 11000011 !emit { rex(w => 1); modrm(mod =>
~MOD_DIRECT); mem(size => 8); }
MOVNTQ SSE 00001111 11100111 !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 8); }
+MOVNTDQ SSE2 00001111 11100111 !emit { data16(); modrm(mod =>
~MOD_DIRECT); mem(size => 16, align => 16); }
PREFETCHT0 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT,
reg => 1); mem(size => 1); }
PREFETCHT1 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT,
reg => 2); mem(size => 1); }
PREFETCHT2 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT,
reg => 3); mem(size => 1); }
PREFETCHNTA SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT,
reg => 0); mem(size => 1); }
+CFLUSH SSE2 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT,
reg => 7); mem(size => 1); }
SFENCE SSE 00001111 10101110 !emit { modrm(mod => MOD_DIRECT, reg
=> 7); }
+LFENCE SSE2 00001111 10101110 !emit { modrm(mod => 0b11, reg =>
0b101); }
+MFENCE SSE2 00001111 10101110 !emit { modrm(mod => 0b11, reg =>
0b111); }
+PAUSE SSE2 10010000 !emit { rep(); }
# State Management Instructions
EMMS MMX 00001111 01110111 !emit { }
--
2.20.1
- Re: [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions, (continued)
[Qemu-devel] [RISU RFC PATCH v2 04/14] risugen_x86: add module, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 07/14] x86.risu: add SSE instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 09/14] x86.risu: add SSE3 instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions,
Jan Bobek <=
[Qemu-devel] [RISU RFC PATCH v2 10/14] x86.risu: add SSSE3 instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 13/14] x86.risu: add AVX instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 14/14] x86.risu: add AVX2 instructions, Jan Bobek, 2019/07/01