[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes |
Date: |
Wed, 7 Aug 2019 00:45:11 -0700 |
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng <address@hidden>
---
Changes in v2: None
hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7557026..9529154 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -77,6 +77,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
char *nodename;
char ethclk_names[] = "pclk\0hclk\0tx_clk";
uint32_t plic_phandle, ethclk_phandle, phandle = 1;
+ uint32_t hfclk_phandle, rtcclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
@@ -95,6 +96,28 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+ hfclk_phandle = phandle++;
+ nodename = g_strdup_printf("/hfclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_HFCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
+ rtcclk_phandle = phandle++;
+ nodename = g_strdup_printf("/rtcclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_RTCCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/memory@%lx",
(long)memmap[SIFIVE_U_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 4abc621..bacd60f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -65,6 +65,8 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
+ SIFIVE_U_HFCLK_FREQ = 33333333,
+ SIFIVE_U_RTCCLK_FREQ = 1000000,
SIFIVE_U_GEM_CLOCK_FREQ = 125000000
};
--
2.7.4
[Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes,
Bin Meng <=
[Qemu-devel] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/07