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Re: [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum numbe
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 |
Date: |
Wed, 7 Aug 2019 11:46:39 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 8/7/19 9:45 AM, Bin Meng wrote:
> It is not useful if we only have one management CPU.
>
> Signed-off-by: Bin Meng <address@hidden>
>
> ---
>
> Changes in v2:
> - update the file header to indicate at least 2 harts are created
>
> hw/riscv/sifive_u.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 821f1d5..91f3c76 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,8 +10,8 @@
> * 1) CLINT (Core Level Interruptor)
> * 2) PLIC (Platform Level Interrupt Controller)
> *
> - * This board currently generates devicetree dynamically that indicates at
> most
> - * five harts.
> + * This board currently generates devicetree dynamically that indicates at
> least
> + * two harts and up to five harts.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -429,6 +429,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
> * management CPU.
> */
> mc->max_cpus = 5;
I'm confuse this patch does not apply on top of v4.1.0-rc4.
Using #define makes these comments redundant, something like:
#define MANAGEMENT_CPU_COUNT 1
#define COMPUTE_CPU_COUNT 4
then you could use
max_cpus = MANAGEMENT_CPU_COUNT + COMPUTE_CPU_COUNT
and
min_cpus = MANAGEMENT_CPU_COUNT + 1.
> + /* It is not useful if we only have one management CPU */
> + mc->min_cpus = 2;
> }
>
> DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
>
- Re: [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, (continued)
- [Qemu-devel] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/07
- [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/07
- Re: [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/07
- Re: [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Alistair Francis, 2019/08/09
[Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/07
[Qemu-devel] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/07