[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu ma
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max |
Date: |
Fri, 16 Aug 2019 14:16:51 +0100 |
From: Alex Bennée <address@hidden>
While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually exist in the reported CPU type.
Avoid this problem by synthesising our own MIDR value.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 6 ++++++
target/arm/cpu64.c | 19 +++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 94c990cddbd..67f2af0e169 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1611,6 +1611,12 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
/*
* System register ID fields.
*/
+FIELD(MIDR_EL1, REVISION, 0, 4)
+FIELD(MIDR_EL1, PARTNUM, 4, 12)
+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
+FIELD(MIDR_EL1, VARIANT, 20, 4)
+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
+
FIELD(ID_ISAR0, SWAP, 0, 4)
FIELD(ID_ISAR0, BITCOUNT, 4, 4)
FIELD(ID_ISAR0, BITFIELD, 8, 4)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1901997a064..ee55237a9b2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -296,6 +296,25 @@ static void aarch64_max_initfn(Object *obj)
uint32_t u;
aarch64_a57_initfn(obj);
+ /*
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a
real
+ * one and try to apply errata workarounds or use impdef features we
+ * don't provide.
+ * An IMPLEMENTER field of 0 means "reserved for software use";
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
+ * to see which features are present";
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
+ * defined and we choose to define PARTNUM just in case guest
+ * code needs to distinguish this QEMU CPU from other software
+ * implementations, though this shouldn't be needed.
+ */
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
+ cpu->midr = t;
+
t = cpu->isar.id_aa64isar0;
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
--
2.20.1
- [Qemu-devel] [PULL 00/29] target-arm queue, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max,
Peter Maydell <=
- [Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption, Peter Maydell, 2019/08/16